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Preliminary Data Sheet March 2000
ORCA(R) ORT4622 Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver
Introduction
Lucent Technologies Microelectronics Group has developed a solution for designers who need the many advantages of FPGA-based design implementation, coupled with high-speed serial backplane data transfer. The 622 Mbits/s backplane transceiver offers a clockless, high-speed interface for interdevice communication on a board or across a backplane. The built-in clock recovery of the ORT4622 allows for higher system performance, easier-todesign clock domains in a multiboard system, and fewer signals on the backplane. Network designers will benefit from the backplane transceiver as a network termination device. The backplane transceiver offers SONET scrambling/descrambling of data and streamlined SONET framing, pointer moving, and transport overhead handling, plus the programmable logic to terminate the network into proprietary systems. For non-SONET applications, all SONET functionality is hidden from the user and no prior networking knowledge is required.
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HSI function uses Lucent Technologies Microelectronics Group's proven 622 Mbits/s serial interface core. Four-channel HSI function provides 622 Mbits/s serial interface per channel for a total chip bandwidth of 2.5 Gbits/s (full duplex). LVDS I/Os compliant with EIA*-644, support hot insertion. 8:1 data multiplexing/demultiplexing for 77.76 MHz byte-wide data processing in FPGA logic. On-chip phase-lock loop (PLL) clock meets B jitter tolerance specification of ITU-T Recommendation G.958 (0.6 UIP-P at 250 kHz). Powerdown option of HSI receiver on a perchannel basis. Highly efficient implementation with only 3% overhead vs. 25% for 8B10B coding. In-Band management and configuration. Streamlined pointer processor (pointer mover) for 8 kHz frame alignment to system clocks. Built-in boundry scan (IEEE 1149.1 JTAG). FIFOs align incoming data across all four channels for STS-48 (2.5 Gbits/s) operation (in quad STS-12 format). 1 + 1 protection supports STS-12/STS-48 redundancy by either software or hardware control for protection switching applications.
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Embedded Core Features
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Implemented in an ORCA Series 3 FPGA array. Allows wide range of applications for SONET network termination application as well as generic data moving for high-speed backplane data transfer. No knowledge of SONET/SDH needed in generic applications. Simply supply data, 78 MHz clock, and a frame pulse. High-speed interface (HSI) function for clock/data recovery serial backplane data transfer without external clocks.
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* EIA is a registered trademark of Electronic Industries Association. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
Table 1. ORCA ORT4622--Available FPGA Logic Device ORT4622 Usable System Gates 60K--120K Number of LUTs 4032 Number of Registers 5304 Max User RAM 64K Max User I/Os 259 Array Size 18 x 28 Number of PFUs 504
The embedded core and interface are not included in the above gate counts. The usable gate count range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates pre-LUT/FF pair (eight per PFU), and 12 gates per SLC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic, CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU.
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Table of Contents
Contents Page Contents Page
Introduction ............................................................... 1 Embedded Core Features ......................................... 1 FPSC Highlights ........................................................ 4 Software Support ...................................................... 4 Description ................................................................ 5 What Is an FPSC? .................................................. 5 FPSC Overview ...................................................... 5 FPSC Gate Counting .............................................. 5 FPGA/Embedded Core Interface ............................ 5 ORCA Foundry Development System .................... 5 FPSC Design Kit ..................................................... 6 FPGA Logic Overview ............................................ 6 PLC Logic ............................................................... 6 PIC Logic ................................................................ 7 System Features .................................................... 7 Routing ................................................................... 7 Configuration .......................................................... 7 More Series 3 Information ...................................... 7 ORT4622 Overview ................................................... 8 Device Layout ......................................................... 8 Backplane Transceiver Interface ............................ 8 HSI Interface ........................................................... 10 STM Macrocell ........................................................ 10 CPU Interface ......................................................... 10 FPGA Interface ....................................................... 10 FPSC Configuration ................................................ 12 Generic Backplane Transceiver Application .............. 13 Backplane Transceiver Core Detailed Description .... 13 HSI Macro ............................................................... 13 STM Transmitter (FPGA -> Backplane) .................. 15 STM Receiver (Backplane -> FPGA) ...................... 19 Powerdown Mode ................................................... 25 Redundancy and Protection Switching ................... 25 Memory Map ............................................................. 26 Definition of Register Types ................................... 26 Memory Map Overview ........................................... 27 Powerup Sequencing for ORT4622 Device .............. 35 FPGA Configuration Data Format ............................. 36 Using ORCA Foundry to Generate Configuration RAM Data ............................................................ 36 FPGA Configuration Data Frame ........................... 36 Bit Stream Error Checking ......................................... 38 FPGA Configuration Modes ...................................... 38 Absolute Maximum Ratings ....................................... 39 Recommend Operating Conditions ........................... 39 Electrical Characteristics ........................................... 40 HSI Circuit Specifications .......................................... 41 Input Data ............................................................... 41 Jitter Tolerance ....................................................... 41 Generated Output Jitter .......................................... 41 PLL ......................................................................... 41 Input Reference Clock ............................................ 41 HSI Circuit Specifications .......................................... 41 Power Supply Decoupling LC Circuit ...................... 42 LVDS I/O ................................................................... 43 LVDS Receiver Buffer Requirements ..................... 44 Timing Characteristics ............................................... 45 Description .............................................................. 45 PFU Timing ............................................................. 46 PLC Timing ............................................................. 46 SLIC Timing ............................................................ 46 PIO Timing .............................................................. 46 Special Function Timing ......................................... 46 Clock Timing ........................................................... 46 Configuration Timing ............................................... 46 Readback Timing .................................................... 46 Input/Output Buffer Measurement Conditions (on-LVDS Buffer) ...................................................... 56 FPGA Output Buffer Characteristics ......................... 57 LVDS Buffer Characteristics ...................................... 58 Termination Resistor ............................................... 58 LVDS Driver Buffer Capabilities .............................. 58 Estimating Power Dissipation .................................... 59 ORT4622 Clock Power ........................................... 59 Pin Information .......................................................... 60 Package Thermal Characteristics Summary ............. 83 JA ......................................................................... 83 JC ......................................................................... 83 JC ......................................................................... 83 JB ......................................................................... 83 FPGA Maximum Junction Temperature ................. 83 Package Thermal Characteristics ............................. 84 Package Coplanarity ................................................. 84 Package Parasitics .................................................... 84 Package Outline Diagrams ........................................ 86 Terms and Definitions ............................................. 86 432-Pin EBGA ........................................................ 87 680-Pin PBGAM ..................................................... 88 Ordering Information ................................................. 90
List of Figures
Figure 1. ORCA ORT4622 Block Diagram ................. 8 Figure 2. Architecture of ORT4622 Backplane Transceiver .............................................................. 11 Figure 3. HSI Functional Block Diagram .................... 14 Figure 4. Byte Ordering of Input/Output Interface in STS-12 Mode........................................................... 15 Figure 5. Interconnect of Streams for FIFO................ 20 Figure 6. Alignment of Four STS-12 Streams ............ 20 Figure 7. Examples of Link Alignment ........................ 21 Figure 8. Pointer Mover State Machine ...................... 22 Figure 9. SPE and C1J1 Functionality ....................... 24 Figure 10. SPE Stuff Bytes......................................... 25 Figure 11. Serial Configuration Data Format-- Autoincrement Mode................................................ 37 2
Lucent Technologies
Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Table of Contents (continued)
Figure Page Table Page
Figure 12. Serial Configuration Data Format-- Explicit Mode............................................................ 37 Figure 13. Sample Power Supply Filter Network for Analog HSI Power Supply Pins................................ 42 Figure 14. Transmit Parallel Port Timing (Backplane -> FPGA)............................................... 48 Figure 15. Transmit Transport Delay (FPGA -> Backplane)............................................... 49 Figure 16. Receive Parallel Port Timing (Backplane -> FPGA)............................................... 50 Figure 17. Protection Switch Timing ........................... 51 Figure 18. TOH Input Serial Port Timing (FPGA -> Backplane)............................................... 52 Figure 19. TOH Output Serial Port Timing (Backplane -> FPGA)............................................... 53 Figure 20. CPU Write Transaction .............................. 54 Figure 21. CPU Read Transaction.............................. 55 Figure 22. ac Test Loads ............................................ 56 Figure 23. Output Buffer Delays ................................. 56 Figure 24. Input Buffer Delays .................................... 56 Figure 25. Sinklim (TJ = 25 C, VDD = 3.3 V).............. 57 Figure 26. Slewlim (TJ = 25 C, VDD = 3.3 V) ............. 57 Figure 27. Fast (TJ = 25 C, VDD = 3.3 V) .................. 57 Figure 28. Sinklim (TJ = 125 C, VDD = 3.0 V)............ 57 Figure 29. Slewlim (TJ = 125 C, VDD = 3.0 V) ........... 57 Figure 30. Fast (TJ = 125 C, VDD = 3.0 V) ................ 57 Figure 31. LVDS Driver and Receiver and Associated Internal Components ............................. 58 Figure 32. LVDS Driver and Receiver......................... 58 Figure 33. LVDS Driver............................................... 58 Figure 34. Package Parasitics .................................... 85
List of Tables
Table 1. ORCA ORT4622--Available FPGA Logic.............................................................. 1 Table 2. ORT4622 Array ............................................ 9 Table 3. Transmitter TOH on LVDS Output (Transparent Mode).................................................. 17 Table 4. Transmitter TOH on LVDS Output (TOH Insert Mode) ................................................... 17 Table 5. Valid Starting Positions for an STS-Mc ........ 21 Table 6. Receiver TOH (Output Parallel Bus)............. 23 Table 7. SPE and C1J1 Functionality ........................ 24 Table 8. Structural Register Elements ...................... 26 Table 9. Memory Map ............................................... 27 Table 10. Memory Map Bit Descriptions .................... 31 Table 11. Configuration Frame Format and Contents................................................................... 37 Table 12. Configuration Modes .................................. 38 Table 13. Absolute Maximum Ratings........................ 39 Table 14. Recommend Operating Conditions ............ 39
Table 15. General Electrical Characteristics ..............39 Table 16. Electrical Characteristics for FPGA I/O.......40 Table 17. Electrical Characteristics for Embedded Core I/O Other than LVDS I/O ..................................40 Table 18. Jitter Tolerance ...........................................41 Table 19. PLL .............................................................41 Table 20. Input Reference Clock ................................41 Table 21. LVDS Driver dc Data ..................................43 Table 22. LVDS Driver ac Data ..................................43 Table 23. LVDS Receiver dc Data .............................44 Table 24. LVDS Receiver ac Data .............................44 Table 25. LVDS Receiver Power Consumption ..........44 Table 26. LVDS Operating Parameters.......................44 Table 27. Derating for Commercial Devices (I/O Supply VDD).......................................................45 Table 28. Derating for Commercial Devices (I/O Supply VDD2).....................................................45 Table 29. ORT4622 Embedded Core and FPGA Interface Clock Operation Frequencies ....................46 Table 30. Timing Requirements (Transmit Parallel Port Timing) ................................................48 Table 31. Timing Requirements (Transmit Transport Delay) .......................................49 Table 32. Timing Requirements (Receive Parallel Port Timing) .................................50 Table 33. Timing Requirements (Protection Switch Timing) ......................................51 Table 34. Timing Requirements (TOH Input Serial Port Timing) ................................52 Table 35. Timing Requirements (TOH Output Serial Port Timing) .............................53 Table 36. Timing Requirements (CPU Write Transaction) ..........................................54 Table 37. Timing Requirements (CPU Read Transaction) ..........................................55 Table 38. Embedded Block Power Dissipation ...........59 Table 39. FPGA Common-Function Pin Description .........................................................60 Table 40. FPSC Function Pin Description ...............63 Table 41. Embedded Core/FPGA Interface Signal Description ...................................................65 Table 42. Embedded Core/FPGA Interface Signal Locations ....................................................67 Table 43. 432-Pin EBGA Pinout .................................68 Table 44. 680-Pin PBGAM Pinout .............................74 Table 45. ORCA ORT4622 Plastic Package Thermal Guidelines ..................................................83 Table 46. ORCA ORT4622 Package Parasitics..........84 Table 47. Voltage Options ..........................................89 Table 48. Temperature Options ..................................89 Table 49. Package Type Options ................................90 Table 50. ORCA Series 3+ Package Matrix ...............90
Lucent Technologies Inc.
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Embedded Core Features
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(continued)
Pseudo-SONET protocol including A1/A2 framing. SONET scrambling and descrambling for required ones density (optional). Selected transport overhead (TOH) bytes insertion and extraction for interdevice communication via the TOH serial link.
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FPSC Highlights
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bined with FPGA logic to create complex functions, such as digital phase-locked loops, frequency counters, and frequency synthesizers or clock doublers. Two PCMs are provided per device. -- True internal 3-state, bidirectional buses with simple control provided by the SLIC. -- 32 x 4 RAM per PFU, configurable as single or dual port. Create large, fast RAM/ROM blocks (128 x 8 in only eight PFUs) using the SLIC decoders as bank drivers. -- Built-in boundary scan (IEEE 1149.1 JTAG) and TS_ALL testability function to 3-state all I/O pins.
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Implemented as an embedded core in the ORCA Series 3+ FPSC architecture. Allows the user to integrate the core with up to 120K gates of programmable logic (all in one device) and provides up to 242 user I/Os in addition to the embedded core I/O pins. FPGA portion retains all of the features of the ORCA Series 3 FPGA architecture: -- High-performance, cost-effective, 0.25 m, 5-level metal technology. -- Twin-quad programmable function unit (PFU) architecture with eight 16-bit look-up tables (LUTs) per PFU, organized in two nibbles for use in nibble- or byte-wide functions. Allows for mixed arithmetic and logic functions in a single PFU. -- Softwired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU. -- Supplemental logic and interconnect cell (SLIC) provides 3-statable buffers, up to 10-bit decoder, and PAL*-like AND-OR-INVERT (AOI) in each programmable logic cell (PLC). -- Up to three ExpressCLK inputs allow extremely fast clocking of signals on- and off-chip plus access to internal general clock routing. -- Dual-use microprocessor interface (MPI) can be used for configuration, as well as for a generalpurpose interface to the FPGA. Glueless interface to i960 and PowerPC processors with userconfigurable address space provided. -- Programmable clock manager (PCM) adjusts clock phase and duty cycle for input clock rates from 5 MHz to 120 MHz. The PCM may be com-
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High-speed, on-chip interface provided between FPGA logic and embedded core to reduce bottlenecks typically found when interfacing off-chip.
Software Support
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Supported by ORCA Foundry software and thirdparty CAE tools for implementing ORCA Series 3+ devices and simulation/timing analysis with the embedded core functions. Embedded core configuration options and simulation netlists generated by FPSC Configuration Manager utility.
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* PAL is a trademark of Advanced Micro Devices, Inc. i960 is a registered trademark of Intel Corporation. PowerPC is a registered trademark of International Business Machines Corporation.
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Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
FPGA/Embedded Core Interface
The interface between the FPGA logic and the embedded core is designed to look like FPGA I/Os from the FPGA side, simplifying interface signal routing and providing a unified approach with general FPGA design. Effectively, the FPGA is designed as if signals were going off of the device to the embedded core, but the on-chip interface is much faster than going off-chip and requires less power. All of the delays for the interface are precharacterized and accounted for in the ORCA Foundry Development System. Clock spines also can pass across the FPGA/embedded core boundary. This allows for fast, low-skew clocking between the FPGA and the embedded core. Many of the special signals from the FPGA, such as DONE and global set/reset, are also available to the embedded core, making it possible to fully integrate the embedded core with the FPGA as a system. For even greater system flexibility, FPGA configuration RAMs are available for use by the embedded core. This allows for user-programmable options in the embedded core, in turn allowing for greater flexibility. Multiple embedded core configurations may be designed into a single device with user-programmable control over which configurations are implemented, as well as the capability to change core functionality simply by reconfiguring the device.
Description
What Is an FPSC?
FPSCs, or field-programmable system chips, are devices that combine field-programmable logic with ASIC or mask-programmed logic on a single device. FPSCs provide the time to market and flexibility of FPGAs, the design effort savings of using soft intellectual property (IP) cores, and the speed, design density, and economy of ASICs.
FPSC Overview
Lucent's Series 3+ FPSCs are created from Series 3 ORCA FPGAs. To create a Series 3+ FPSC, several rows of programmable logic cells (see FPGA Logic Overview section for FPGA logic details) are removed from a Series 3 ORCA FPGA, and the area is replaced with an embedded logic core. Other than replacing some FPGA gates with ASIC gates, at greater than 10:1 efficiency, none of the FPGA functionality is changed--all of the Series 3 FPGA capability is retained: MPI, PCMs, boundary scan, etc. The rows of programmable logic are replaced at the bottom of the device, allowing pins on the bottom and sides of the replaced rows to be used as I/O pins for the embedded core. The remainder of the device pins retain their FPGA functionality as do special function FPGA pins within the embedded core area. The embedded cores can take many forms and generally come from Lucent Technologies ASIC libraries. Other offerings allow customers to supply their own core functions for the creation of custom FPSCs.
ORCA Foundry Development System
The ORCA Foundry Development System is used to process a design from a netlist to a configured FPSC. This system is used to map a design onto the ORCA architecture and then place and route it using ORCA Foundry's timing-driven tools. The development system also includes interfaces to, and libraries for, other popular CAE tools for design entry, synthesis, simulation, and timing analysis. The ORCA Foundry Development System interfaces to front-end design entry tools and provides the tools to produce a configured FPSC. In the design flow, the user defines the functionality of the FPGA portion of the FPSC and embedded core settings at two points in the design flow: at design entry and at the bit stream generation stage. Following design entry, the development system's map, place, and route tools translate the netlist into a routed FPSC. A static timing analysis tool is provided to determine device speed, and a backannotated netlist can be created to allow simulation.
FPSC Gate Counting
The total gate count for an FPSC is the sum of its embedded core (standard-cell/ASIC gates) and its FPGA gates. Because FPGA gates are generally expressed as a usable range with a nominal value, the total FPSC gate count is sometimes expressed in the same manner. Standard-cell ASIC gates are, however, 10 to 25 times more silicon area efficient than FPGA gates. Therefore, an FPSC with an embedded function is gate equivalent to an FPGA with a much larger gate count.
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Description (continued)
Timing and simulation output files from ORCA Foundry are also compatible with many third-party analysis tools. Its bit stream generator is then used to generate the configuration data which is loaded into the FPSC's internal configuration RAM. When using the bit stream generator, the user selects options that affect the functionality of the FPSC. Combined with the front-end tools, ORCA Foundry produces configuration data that implements the various logic and routing options discussed in this data sheet.
FPSC Design Kit
Development is facilitated by an FPSC design kit which, together with ORCA Foundry and third-party synthesis and simulation engines, provides all software and documentation required to design and verify an FPSC implementation. Included in the kit are the FPSC configuration manager, HDL gate-level structural netlists, all necessary synthesis libraries, and complete online documentation. The kit's software couples with ORCA Foundry, providing a seamless FPSC design environment. More information can be obtained by visiting the ORCA website or contacting a local sales office, both listed on the last page of this document.
ORCA Series 3 FPGA logic consists of three basic elements: programmable logic cells (PLCs), programmable input/output cells (PICs), and system-level features. An array of PLCs is surrounded by PICs. Each PLC contains a programmable function unit (PFU), a supplemental logic and interconnect cell (SLIC), local routing resources, and configuration RAM. Most of the FPGA logic is performed in the PFU, but decoders, PAL-like functions, and 3-state buffering can be performed in the SLIC. The PICs provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplexing, and other functions on two output signals. Some of the system-level functions include the new microprocessor interface (MPI) and the programmable clock manager (PCM).
PLC Logic
Each PFU within a PLC contains eight 4-input (16-bit) look-up tables (LUTs), eight latches/flip-flops (FFs), and one additional flip-flop that may be used independently or with arithmetic functions. The PFU is organized in a twin-quad fashion: two sets of four LUTs and FFs that can be controlled independently. LUTs may also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit modes. The carry-out of either mode may be registered in the ninth FF for pipelining. Each PFU may also be configured as a synchronous 32 x 4 single- or dual-port RAM or ROM. The FFs (or latches) may obtain input from LUT outputs or directly from invertible PFU inputs, or they can be tied high or tied low. The FFs also have programmable clock polarity, clock enables, and local set/reset. The SLIC is connected to PLC routing resources and to the outputs of the PFU. It contains 3-state, bidirectional buffers and logic to perform up to a 10-bit AND function for decoding, or an AND-OR with optional INVERT (AOI) to perform PAL-like functions. The 3-state drivers in the SLIC and their direct connections to the PFU outputs make fast, true 3-state buses possible within the FPGA logic, reducing required routing and allowing for real-world system performance.
FPGA Logic Overview
ORCA Series 3 FPGA logic is a new generation of SRAM-based FPGA logic built on the successful Series 2 FPGA line from Lucent Technologies Microelectronics Group, with enhancements and innovations geared toward today's high-speed designs on a single chip. Designed from the start to be synthesis friendly and to reduce place and route times while maintaining the complete routability of the ORCA Series 2 devices, the Series 3 more than doubles the logic available in each logic block and incorporates system-level features that can further reduce logic requirements and increase system speed. ORCA Series 3 devices contain many new patented enhancements and are offered in a variety of packages, speed grades, and temperature ranges.
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Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Routing
The abundant routing resources of ORCA Series 3 FPGA logic are organized to route signals individually or as buses with related control signals. Clocks are routed on a low-skew, high-speed distribution network and may be sourced from PLC logic, externally from any I/O pad, or from the very fast ExpressCLK pins. ExpressCLKs may be glitchlessly and independently enabled and disabled with a programmable control signal using the StopCLK feature. The improved PIC routing resources are now similar to the patented intra-PLC routing resources and provide great flexibility in moving signals to and from the PIOs. This flexibility translates into an improved capability to route designs at the required speeds when the I/O signals have been locked to specific pins.
Description (continued)
PIC Logic
The Series 3 PIC addresses the demand for everincreasing system clock speeds. Each PIC contains four programmable inputs/outputs (PIOs) and routing resources. On the input side, each PIO contains a fastcapture latch that is clocked by an ExpressCLK. This latch is followed by a latch/FF that is clocked by a system clock from the internal general clock routing. The combination provides for very low setup requirements and zero hold times for signals coming on-chip. It may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the signals without explicitly building a demultiplexer. Two input signals are available to the PLC array from each PIO, and the ORCA Series 2 capability to use any input pin as a clock or other global input is maintained. On the output side of each PIO, two outputs from the PLC array can be routed to each output flip-flop, and logic can be associated with each I/O pad. The output logic associated with each pad allows for multiplexing of output signals and other functions of two output signals. The output FF, in combination with output signal multiplexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. The I/O buffer associated with each pad is the same as the ORCA Series 3 buffer.
Configuration
The FPGA logic's functionality is determined by internal configuration RAM. The FPGA logic's internal initialization/configuration circuitry loads the configuration data at powerup or under system control. The RAM is loaded by using one of several configuration modes, including serial EEPROM, the microprocessor interface, or the embedded function core.
More Series 3 Information
For more information on Series 3 FPGAs, please refer to the Series 3 FPGA data sheet, available on the ORCA worldwide website or by contacting Lucent Technologies as directed on the back of this data sheet.
System Features
The Series 3 also provides system-level functionality by means of its dual-use microprocessor interface (MPI) and its innovative programmable clock manager (PCM). These functional blocks allow for easy glueless system interfacing and the capability to adjust to varying conditions in today's high-speed systems. Since these and all other Series 3 features are available in every Series 3+ FPSC, they can also interface to the embedded core providing for easier system integration.
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
ORT4622 Overview
Device Layout
The ORT4622 FPSC provides a high-speed backplane transceiver combined with FPGA logic. The device is based on a 2.5 V 3.3 V I/O OR3L125B FPGA. The OR3L125B has a 28 x 28 array of programmable logic cells (PLCs). For the ORT4622, the bottom ten rows of PLCs in the array were replaced with the embedded backplane transceiver core. The ORT4622 embedded core comprises the HSI macrocell, the synchronous transport module (STM) macrocell, a CPU interface, and LVDS I/Os. The four full-duplex channels perform data transfer, scrambling/descrambling and framing at the rate of 622 Mbits/s. Figure 1 shows the ORT4622 block diagram. Table 2 shows a schematic view of the ORT4622. The upper portion of the device is an 18 x 28 array of PLCs surrounded on the left, top, and right by programmable input/output cells (PICs). At the bottom of the PLC array are the core interface cells (CICs) connecting to the embedded core region. The embedded core region contains the backplane transceiver functionality of the device. It is surrounded on the left, bottom, and right by backplane transceiver dedicated I/Os as well as power and special function FPGA pins. Also shown are the interquad routing blocks (hIQ, vIQ) present in the Series 3 FPGA devices. System-level functions (located in the corners of the PLC array), routing resources, and configuration RAM are not shown in Table 2.
Backplane Transceiver Interface
The advantage of the ORT4622 FPSC is to bring specific networking functions to an early market presence with programmable logic in FPGA system. The 622 Mbits/s backplane transceiver core allows the ORT4622 to communicate across a backplane or on a given board at an aggregate speed of 2.5 Gbits/s, providing a physical medium for high-speed asynchronous serial data transfer between system devices. This device is intended for, but not limited to, connecting terminal equipment in SONET/SDH and ATM systems. For networking applications, the ORT4622 offers a pseudo SONET framer and scrambler/descrambler interface capable of frame synchronization and insertion/extraction of selectable transport overhead bytes and SONET scrambling and descrambling for four STS-12 (622 Mbits/s) channels. The channels are synchronized to each other by a user-provided 8 kHz frame pulse. The ORT4622 also provides STS-48 (2.5 Gbits/s) operation across all four channels where each channel is in STS-12 format. The pseudo-SONET framer of OR4622 is designed with a reduced set of the SONET framing algorithm. The pointer processing capability is more suitable for low error rate intersystem data communication, particular for backplane transceiver applications. Figure 2 shows the architecture of the ORT4622 backplane transceiver core.
622 Mbits/s DATA 4
HSI
STM
4 FULLDUPLEX SERIAL CHANNELS 4 622 Mbits/s DATA
LVDS I/Os
* CLOCK/DATA RECOVERY
BYTEWIDE DATA
* POINTER MOVER * SCRAMBLING * FIFO ALIGNMENT * TOH PROCESSOR
FPGA LOGIC
STANDARD FPGA I/Os
5-8113(F)
Figure 1. ORCA ORT4622 Block Diagram
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Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
ORT4622 Overview (continued)
Table 2. ORT4622 Array IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII
PT1 PT2 R1 C2 R2 C2 R3 C2 R4 C2 R5 C2 R6 C2 R7 C2 R8 C2 R9 C2 R10 C2 R11 C2 R12 C2 R13 C2 R14 C2 PT3 R1 C3 R2 C3 R3 C3 R4 C3 R5 C3 R6 C3 R7 C3 R8 C3 R9 C3 R10 C3 R11 C3 R12 C3 R13 C3 R14 C3 PT4 R1 C4 R2 C4 R3 C4 R4 C4 R5 C4 R6 C4 R7 C4 R8 C4 R9 C4 R10 C4 R11 C4 R12 C4 R13 C4 R14 C4 PT5 R1 C5 R2 C5 R3 C5 R4 C5 R5 C5 R6 C5 R7 C5 R8 C5 R9 C5 R10 C5 R11 C5 R12 C5 R13 C5 R14 C5 PT6 R1 C6 R2 C6 R3 C6 R4 C6 R5 C6 R6 C6 R7 C6 R8 C6 R9 C6 R10 C6 R11 C6 R12 C6 R13 C6 R14 C6 PT7 R1 C7 R2 C7 R3 C7 R4 C7 R5 C7 R6 C7 R7 C7 R8 C7 R9 C7 R10 C7 R11 C7 R12 C7 R13 C7 R14 C7 PT8 R1 C8 R2 C8 R3 C8 R4 C8 R5 C8 R6 C8 R7 C8 R8 C8 R9 C8 R10 C8 R11 C8 R12 C8 R13 C8 R14 C8 PT9 R1 C9 R2 C9 R3 C9 R4 C9 R5 C9 R6 C9 R7 C9 R8 C9 R9 C9 R10 C9 R11 C9 R12 C9 R13 C9 R14 C9 PT10 R1 C10 R2 C10 R3 C10 R4 C10 R5 C10 R6 C10 R7 C10 R8 C10 R9 C10 R10 C10 R11 C10 R12 C10 R13 C10 R14 C10 PT11 R1 C11 R2 C11 R3 C11 R4 C11 R5 C11 R6 C11 R7 C11 R8 C11 R9 C11 R10 C11 R11 C11 R12 C11 R13 C11 R14 C11 PT12 R1 C12 R2 C12 R3 C12 R4 C12 R5 C12 R6 C12 R7 C12 R8 C12 R9 C12 R10 C12 R11 C12 R12 C12 R13 C12 R14 C12 PT13 R1 C13 R2 C13 R3 C13 R4 C13 R5 C13 R6 C13 R7 C13 R8 C13 R9 C13 R10 C13 R11 C13 R12 C13 R13 C13 R14 C13 PT14 R1 C14 R2 C14 R3 C14 R4 C14 R5 C14 R6 C14 R7 C14 R8 C14 R9 C14 R10 C14 R11 C14 R12 C14 R13 C14 R14 C14
IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII
PT15 R1 C15 R2 C15 R3 C15 R4 C15 R5 C15 R6 C15 R7 C15 R8 C15 R9 C15 R10 C15 R11 C15 R12 C15 R13 C15 R14 C15 PT16 R1 C16 R2 C16 R3 C16 R4 C16 R5 C16 R6 C16 R7 C16 R8 C16 R9 C16 R10 C16 R11 C16 R12 C16 R13 C16 R14 C16 PT17 R1 C17 R2 C17 R3 C17 R4 C17 R5 C17 R6 C17 R7 C17 R8 C17 R9 C17 R10 C17 R11 C17 R12 C17 R13 C17 R14 C17 PT18 R1 C18 R2 C18 R3 C18 R4 C18 R5 C18 R6 C18 R7 C18 R8 C18 R9 C18 R10 C18 R11 C18 R12 C18 R13 C18 R14 C18 PT19 R1 C19 R2 C19 R3 C19 R4 C19 R5 C19 R6 C19 R7 C19 R8 C19 R9 C19 R10 C19 R11 C19 R12 C19 R13 C19 R14 C19 PT20 R1 C20 R2 C20 R3 C20 R4 C20 R5 C20 R6 C20 R7 C20 R8 C20 R9 C20 R10 C20 R11 C20 R12 C20 R13 C20 R14 C20 PT21 R1 C21 R2 C21 R3 C21 R4 C21 R5 C21 R6 C21 R7 C21 R8 C21 R9 C21 R10 C21 R11 C21 R12 C21 R13 C21 R14 C21 PT22 R1 C22 R2 C22 R3 C22 R4 C22 R5 C22 R6 C22 R7 C22 R8 C22 R9 C22 R10 C22 R11 C22 R12 C22 R13 C22 R14 C22 PT23 R1 C23 R2 C23 R3 C23 R4 C23 R5 C23 R6 C23 R7 C23 R8 C23 R9 C23 R10 C23 R11 C23 R12 C23 R13 C23 R14 C23 PT24 R1 C24 R2 C24 R3 C24 R4 C24 R5 C24 R6 C24 R7 C24 R8 C24 R9 C24 R10 C24 R11 C24 R12 C24 R13 C24 R14 C24 PT25 R1 C25 R2 C25 R3 C25 R4 C25 R5 C25 R6 C25 R7 C25 R8 C25 R9 C25 R10 C25 R11 C25 R12 C25 R13 C25 R14 C25 PT26 R1 C26 R2 C26 R3 C26 R4 C26 R5 C26 R6 C26 R7 C26 R8 C26 R9 C26 R10 C26 R11 C26 R12 C26 R13 C26 R14 C26 PT27 R1 C27 R2 C27 R3 C27 R4 C27 R5 C27 R6 C27 R7 C27 R8 C27 R9 C27 R10 C27 R11 C27 R12 C27 R13 C27 R14 C27 PT28
IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII
IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII
R1 C1 R2 C1 R3 C1 R4 C1 R5 C1 R6 C1 R7 C1 R8 C1 R9 C1 R10 C1 R11 C1 R12 C1 R13 C1 R14 C1
R1 C28 R2 C28 R3 C28 R4 C28 R5 C28 R6 C28 R7 C28 R8 C28 R9 C28 R10 C28 R11 C28 R12 C28 R13 C28 R14 C28
PR1
PL1
PR2
PL2
PR3
PL3
PR4
PL4
PR5
PL5
PR6
PL6
PR7
PL7
PR8
PL8
PR9
PL9
PR10
PL10
PR11
PL11
PR12
PL12
PR13
PL13
PR14
IIII IIII IIII IIII IIII IIII IIII IIII IIII II II IIII IIII IIII IIII
PL14
IIII IIII IIII IIII II II IIII IIII IIII IIII IIII IIII IIII IIII IIII
PR15
PL15
R15 C1 R16 C1 R17 C1 R18 C1 ASB1
R15 C2 R16 C2 R17 C2 R18 C2 ASB2
R15 C3 R16 C3 R17 C3 R18 C3 ASB3
R15 C4 R16 C4 R17 C4 R18 C4 ASB4
R15 C5 R16 C5 R17 C5 R18 C5 ASB5
R15 C6 R16 C6 R17 C6 R18 C6 ASB6
R15 C7 R16 C7 R17 C7 R18 C7 ASB7
R15 C8 R16 C8 R17 C8 R18 C8 ASB8
R15 C9 R16 C9 R17 C9 R18 C9 ASB9
R15 C10 R16 C10 R17 C10 R18 C10 ASB10
R15 C11 R16 C11 R17 C11 R18 C11 ASB11
R15 C12 R16 C12 R17 C12 R18 C12 ASB12
R15 C13 R16 C13 R17 C13 R18 C13 ASB13
R15 C14 R16 C14 R17 C14 R18 C14 ASB14
R15 C15 R16 C15 R17 C15 R18 C15 ASB15
R15 C16 R16 C16 R17 C16 R18 C16 ASB16
R15 C17 R16 C17 R17 C17 R18 C17 ASB17
R15 C18 R16 C18 R17 C18 R18 C18 ASB18
R15 C19 R16 C19 R17 C19 R18 C19 ASB19
R15 C20 R16 C20 R17 C20 R18 C20 ASB20
R15 C21 R16 C21 R17 C21 R18 C21 ASB21
R15 C22 R16 C22 R17 C22 R18 C22 ASB22
R15 C23 R16 C23 R17 C23 R18 C23 ASB23
R15 C24 R16 C24 R17 C24 R18 C24 ASB24
R15 C25 R16 C25 R17 C25 R18 C25 ASB25
R15 C26 R16 C26 R17 C26 R18 C26 ASB26
R15 C27 R16 C27 R17 C27 R18 C27 ASB27
R15 C28 R16 C28 R17 C28 R18 C28 ASB28
PR16
PL16
PR17
PL17
PR18
PL18
EMBEDDED CORE AREA
IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII
IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII
Lucent Technologies Inc. Lucent Technologies Inc.
9
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
ORT4622 Overview (continued)
HSI Interface
The high-speed interconnect (HSI) macrocell is used for clock/data recovery and MUX/deMUX between 77.76 MHz byte-wide internal data buses and 622 Mbits/s external serial links. The HSI interface receives four 622 Mbits/s serial input data streams from the LVDS inputs and provides four independent 77.76 MHz byte-wide data streams and recovered clock to the STM macro. There is no requirement for bit alignment since SONET type framing will take place inside the ORT4622 core. For transmit, the HSI converts four byte-wide 77.76 MHz data streams to serial streams at 622 Mbits/s at the LVDS outputs.
CPU Interface
The embedded core has a dedicated, asynchronous, MPC860 compatible, CPU interface that is used for device setup, control, and monitoring. Dual sets of I/O pins of this CPU interface with a bit stream configurable scheme provide designers a convenient and flexible option for configuration. One set of CPU I/O pins goes off chip allowing direct connection with an onboard CPU. Another set of CPU I/O pins is available to the FPGA logic allowing for a stand-alone system free of an external CPU interface, or for itegration into the Series 3 FPGA MPI interface. The CPU interface is composed of an 8-bit data bus, a 7-bit address bus, a chip select signal, a read/write signal, and an interrupt signal.
FPGA Interface STM Macrocell
The STM portion of the embedded core consists of transmitter (Tx) and receiver (Rx) sections. The receiver receives four byte-wide data streams at 77.76 MHz and the associated clocks from the HSI. In the Rx section, the incoming streams are SONET framed and descrambled before they are written into a FIFO which absorbs phase and delay variations and allows the shift to the system clock. The TOH is then extracted and sent out on the four serial ports. The pointer Mover consists of three blocks: pointer interpreter, elastic store, and pointer generator. The pointer interpreter finds the synchronous transport signal (STS) synchronous payload envelopes (SPE) and places it into a small elastic store from which the pointer generator will produce four byte-wide STS-12 streams of data that are aligned to the system timing pulse. In the Tx section, transmitted data for each channel is received through a parallel bus and a serial port from the FPGA circuit. TOH bytes are received from the serial input port and can be optionally inserted from programmable registers or serial inputs to the STS-12 frame via the TOH processor. Each of the four parallel input buses is synchronized to a free-running system clock. Then the SPE and TOH data is transferred to the HSI. The STM macrocell also has a scrambler/descrambler disable feature, allowing the user to disable the scrambler of the transmitter and the descrambler of the receiver. Also, unused channels can be disabled to reduce power dissipation. The FPGA logic will receive/transmit frame-aligned streams of 77.76 MHz data (maximum of four streams in each direction) from/to the backplane transceiver embedded core. All frames transmitted to the FPGA will be aligned to the FPGA frame pulse which will be provided by the FPGA user's logic to the STM macro. All frames received from the FPGA logic will be aligned to the system frame pulse that will be supplied to the STM macro from the FPGA user's logic.
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Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
ORT4622 Overview (continued)
TOH CLK TX TOH CLK EN LINE LBPK (SOFT CTL) TOH TX A TX BUS A 9 TO RX TOH PROC. QUAD CHANNEL TRANSMITTER TX TOH PROCESSOR FRAME PROC. TX CH A (MACRO) 2
LVDS OUT A
TOH TX B TX BUS B 9
TX TOH PROCESSOR FRAME PROC. TX CH B (MACRO)
2
LVDS OUT B
TOH TX C TX BUS C 9
TX TOH PROCESSOR FRAME PROC. TX CH C (MACRO)
2
LVDS OUT C
TOH TX D TX BUS D 9
TX TOH PROCESSOR FRAME PROC. TX CH D (MACRO) 77.76 MHz 77.76 MHz /8 PLL 622 MHz Clks
2
LVDS OUT D
LINE FRAME PROT SWITCH A/B FPGA I/F SIGNALS SOFT CTL SOFT CTL 12 DATA RX BUS A DATA RX A EN CH B SOFT CTL 12 DATA RX BUS B DATA RX B EN PROT SWITCH C/D SOFT CTL SOFT CTL 12 DATA RX BUS C DATA RX C EN CH D SOFT CTL DATA RX BUS D DATA RX D EN TOH_EN TOH RX A TOH RX B CH B
SOFT CTL SOFT CTL
FRAME CLOCK CH A
FDBK REF
RX CH A 77.76 (MACROCELL) MHz
2
LVDS IN A
POINTER MOVER STS48 FIFO
77.76 MHz
RX CH B (MACROCELL)
2
LVDS IN B
CH C
77.76 MHz
RX CH C (MACROCELL)
2
LVDS IN C
12
TOH CLK
SOFT CTL
77.76 MHz
RX CH D (MACROCELL)
2
LVDS IN D
CH A
LVDS LPBK (SOFT CTL)
CH C TOH RX C TOH RX D RX TOH CLK FPEN RX TOH CLK EN RX TOH FRAME SOFT CTL CH D
RX TOH PROCESSOR
QUAD CHANNEL RECEIVER
CPU INTERFACE (ASYNC) ADDR DATA RST_N RD/WR_N 7 8 INT_N CS_N
DEVICE I/O OR FPGA I/F SIGNALS (BIT STREAM SELECTABLE) 5-8576 (F)
Figure 2. Architecture of ORT4622 Backplane Transceiver Lucent Technologies Inc. Lucent Technologies Inc. 11
DEVICE I/O
SYSTEM FRAME SYSTEM CLOCK
622 MHz
SYSTEM CLOCK (77.76 MHz)
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
ORT4622 Overview (continued)
FPSC Configuration
Configuration of the ORT4622 occurs in two stages, FPGA bit stream configuration and embedded core setup. FPGA Configuration Prior to becoming operational, the FPGA goes through a sequence of states, including powerup initialization, configuration, start-up, and operation. The FPGA logic is configured by standard FPGA bit stream configuration means as discussed in the Series 3 FPGA data sheet. Additionally, for the ORT4622, the location of the CPU interface to the embedded core, either on the device pins or at the FPGA/embedded core boundary, is configured via FPGA configuration and is defined via the ORT4622 design kit. The default configuration sets the CPU interface pins to be active. A simple microprocessor emulation soft Intellectual Property (IP) core that uses very small FPGA logic is available from Lucent. This microprocessor core sets up the embedded core via a state machine and allows the ORT4622 to work in an independent system without an external microprocessor interface. Embedded Core Setup The embedded core operation is set up via the embedded core CPU interface. All options for the operation of the core are configured according to the device register map presented in the detailed description section of this data sheet. During the powerup sequence, the ORT4622 device (FPGA programmable circuit and the core) is held in reset. All the LVDS output buffers and other output buffers are held in 3-state. All flip-flops in core area are in reset state, with the exception of the boundry scan shift registers, which can only be reset by Boundary Scan Reset. After powerup reset, the FPGA can start configuration. During FPGA configuration, the ORT4622 core will be held in reset and all the local bus interface signals are forced high, but the following active-high signals (PROT_SWITCH_A, PROT_SWITCH_C, TX_TOH_CK_EN, SYS_FP, LINE_FP) are forced low. The CORE_READY signal sent from the embedded core to FPGA is held low, indi-
cating core is not ready to interact with FPGA logic. At the end of the FPGA configuration sequence, the CORE_READY signal will be held low for six SYS_CLK cycles after DONE, TRI_IO and RST_N (core global reset) are high. Then it will go active-high, indicating the embedded core is ready to function and interact with FPGA programmable circuit. During FPGA reconfiguration when DONE and TRI_IO are low, the CORE_READY signal sent from the core to FPGA will be held low again to indicate the embedded core is not ready to interact with FPGA logic. During FPGA partial configuration, CORE_READY stays active. The same FPGA configuration sequence described previously will repeat again. The initialization of the embedded core consists of two steps: register configuration and synchronization of the alignment FIFO. In order to configure the embedded core, the registers need to be unlocked by writing 0xA0 to address 0x04 and writing 0x01 to address 0x05. Control registers 0x04 and 0x05 are lock registers. If the output bus of the data, serial TOH port, and TOH clock and TOH frame pulse are controlled by 3-state registers (the use of the registers for 3-state output control is optional; these output 3-state enable signals are brought across the local bus interface and available to the FPGA side), the next step is to activate the 3state output bus and signals by taking them to functional state from high-impedance state. This can be done by writing 0x01 to correspond bits of the channel registers 0x20, 0x38, 0x50, and 0x68. If the 3-state control is done in FPGA logic or external logic instead of in the embedded core registers, this step should be done in that particular control logic also. In addition, the synchronization of selected streams is recommended for some networking systems applications. This is a resync of the alignment FIFO after the enabled channels have a valid frame pulse. Here are the procedures: Put all of the streams to be aligned, including disabled streams, into their required alignment mode. Force AIS-L in all streams to be synchronized (refer to register map, write 0x01 to DB1 of register 0x20, 0x38, 0x50, 0x68). Wait four frames. Write a 0x01 to the FIFO alignment resync register, bit DB1 of register 0x06. Wait four frames. Release the AIS-L in all streams (write 1 to DB1 of register 0x20, 0x38, 0x50, 0x68). This procedures allows normal data flow through the embedded core.
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Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Generic Backplane Transceiver Application
The combination of ORT4622 and soft IP cores provides a generic data moving solution for non-SONET applications. There is no requirement for SONET knowledge to the users. All that is needed is to supply the embedded core interface with data, clock, and a 8 kHz frame pulse. The provision registers may also need to be set up, and this can be done through either the FPGA MPI or in a state machine in the FPGA section (VHDL code available from Lucent). The 8 kHz frame pulse must be supplied to the SYS_FP signal. For generic applications, the frame pulse can be created in FPGA logic from the 77.76 MHz SYS_CLK using a simple resettable counter (the frame pulse should only be high for one cycle of the SYS_CLK). A VHDL core that automatically provides the 8 kHz frame pulse is available from Lucent. Byte-wide data is then sent to each of the transmit channels as follows: the first 36 bytes transferred will be invalid data (replaced by overhead), where the first byte is sent on the rising edge of SYS_CLK when SYS_FP is high. The next 1044 byte positions can be filled with valid data. This will repeat a total of nine times (36 invalid bytes followed by 1044 valid bytes) at which time the next 8 kHz frame pulse will be found. Thus, 87 out of 90 (96.7%) of the data bytes sent are valid user data. On the receive side, an 8 kHz pulse must again be supplied to SYS_FP. In this case, however, only the signal DATA_RX*_SPE must be monitored for each channel, where a high value on this signal means valid data. Again 87 out 90 bytes received (96.7%) will be valid data. In order to provide an easy user interface to transfer arbitrary data streams through the ORT4622, Lucent provides a soft Intellectual Property (IP) core called the protocol independent framer, or PI-Framer. This block transfers user format to the one described above and allows for smoothing/rate transfer of this user data. This framer works with a single channel at 622 Mbits/s, two channels at 1.25 Gbits/s, or across four channels at 2.5 Gbits/s.
Backplane Transceiver Core Detailed Description
HSI Macro
The high-speed interface (HSI) provides a physical medium for high-speed asynchronous serial data transfer between the ORT4622 and other devices. The devices can be mounted on the same board or mounted on different boards and connected through the shelf backplane. The 622 Mbits/s CDR macro is a four-channel clock phase select (CPS) and data retime function with serial-to-parallel demultiplexing for the incoming data stream and parallel-to-serial multiplexing for outgoing data. The HSI macro consists of three functionally independent blocks: receiver, transmitter, and PLL synthesizer as shown in Figure 3. The PLL synthesizer block receives a 77.76 MHz reference clock at its input, and provides a phase-locked 622.08 MHz clock to the transmitter block and phase control signal to the receiver block. The PLL synthesizer block is a common asset shared by four receive and transmit channels. The HSI receiver receives four channels of differential 622.08 Mbits/s serial data without clock at its LVDS receive inputs. The received data must be scrambled, conforming to SONET STS-12 and SDH STM-4 data formats using either a PN7 or PN9 sequence. The PN7 characteristic polynomial is 1 + x6 + x7, and PN9 characteristic polynomial is 1 + x4 + x9. The ORT4622 supplies a default scrambler using the PN7 sequence. The clock phase select and data retime (CPS/DR) module performs a clock recovery and data retiming function by using phase control information. The resultant 622.08 Mbits/s data and clock are then passed to the deserializer module, which performs serial-to-parallel conversion and provides a 77.76 Mbits/s parallel data and clock at its output. The HSI transmitter receives four channels of 77.76 Mbits/s parallel data that is synchronous to the reference clock at its inputs. The serializer performs a parallel-to-serial conversion using a 622.08 MHz clock provided by the PLL/synthesizer block. The 622 Mbits/s serial data streams are then transmitted through the LVDS drivers.
Lucent Technologies Inc. Lucent Technologies Inc.
13
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Backplane Transceiver Core Detailed Description (continued)
LVDS HDIN 622 Mbits/s SELECT DEMUX 622 Mbits/s SERIAL TO 78 MHz PARALLEL 622 Mbits/s DATA BUFFER 50 50 CLOCK/DATA ALIGNMENT 622 Mbits/s DATA 8 (77.76 Mbits/s DATA)
LOOPBKEN HSI_RX LOOPBACK
PHASE ADJUSTMENT
622 MHz CLOCK
(77.76 MHz CLOCK)
(77.76 MHz REF CLOCK) REF78 REXT (RESISTOR) 622.08 MHz PLL SYNTHESIZER
622.08 MHz CLOCK 77.76 MHz MUX 78 MHz PARALLEL TO 622 Mbits/s SERIAL LOOPBACK BS-MUX
622 Mbits/s DATA
100 LVDS BUFFER
8 (77.76 Mbytes DATA)
HDOUT 622 Mbits/s
77.76 Mbytes DATA
HSI_TX
BOUNDARYSCAN CONTROL
BSCANEN
5-8592 (F)
Figure 3. HSI Functional Block Diagram
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Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
data communication channel (DCC, D1--D3) and line data communication channel (DCC, D4--D12) insertion (for intercard communications channel); scrambling of outgoing data stream with optional scrambler disabling; and optional stream disabling. When the ORT4622 is used in nonnetworking applications as a generic high-speed backplane data mover, the TOH serial ports are unused or can be used for slow-speed off-channel communication between devices. Data received on the parallel bus is optionally scrambled and transferred to LVDS outputs. Byte Ordering Information The core supports quad STS-12 mode of operation on the input/output ports. STS-48 is also supported when received in quad STS-12 format. When operating in quad STS-12 mode, each of the independent byte streams carries an entire STS-12 within it. Figure 4 reveals the byte ordering of the individual STS-12 streams and for STS-48 operation. Note that the recovered data will always continue to be in the same order as transmitted.
Backplane Transceiver Core Detailed Description (continued)
STM Transmitter (FPGA -> Backplane)
The STM has four STS-12 transmit channels which can be treated as a single STS-48 channel. In general, the transmitter circuit receives four byte-wide 77.76 MHz data from the FPGA, which nominally represents four STS-12 streams (A, B, C, and D). This data is synchronized to the system (reference) clock, and an 8 kHz system frame pulse from the FPGA logic. Transport overhead bytes are then optionally inserted into these streams, and the streams are forwarded to the HSI. All byte timing pulses required to isolate individual overhead bytes (e.g., A1, A2, B1, D1--D3, etc.) are generated internally based on the system frame pulse (SYS_FP) received from the FPGA logic. All streams operate byte-wide at 77.76 MHz in all modes. The TOH processor operates from 25 MHz to 77.76 MHz and supports the following TOH signals: A1 and A2 insertion and optional corruption; H1, H2, and H3 pass transparently; BIP-8 parity calculation (after scrambling) and B1 byte insertion and optional corruption (before scrambling); optional K1 and K2 insert; optional S1/M0 insert; optional E1/F1/E2 insert; optional section
12 24 36 48
9 21 33 45
6 18 30 42
3 15 27 39
11 23 35 47
8 20 32 44
5 17 29 41
2 14 26 38
10 22 34 46
7 19 31 43
4 16 28 40
1 13 25 37
STS-12 A STS-12 B STS-12 C STS-12 D
STS-48 IN QUAD STS-12 FORMAT
1, 12 1, 9 2, 12 2, 9 3, 12 3, 9 4, 12 4, 9 QUAD STS-12
1, 6 2, 6 3, 6 4, 6
1, 3 1, 11 1, 8 2, 3 2, 11 2, 8 3, 3 3, 11 3, 8 4, 3 4, 11 4, 8
1, 5 2, 5 3, 5 4, 5
1, 2 1, 10 1, 7 2, 2 2, 10 2, 7 3, 2 3, 10 3, 7 4, 2 4, 10 4, 7
1, 4 2, 4 3, 4 4, 4
1, 1 2, 1 3, 1 4, 1
STS-12 A STS-12 B STS-12 C STS-12 D
5-8574 (F)
Figure 4. Byte Ordering of Input/Output Interface in STS-12 Mode
Lucent Technologies Inc. Lucent Technologies Inc.
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Backplane Transceiver Core Detailed Description (continued)
Transport Overhead for In Band Communication The TOH byte can be used for In Band configuration, service, and management since it is carried along the same channel as data. In ORT4622, In Band signaling can be efficiently utilized, since the total cost of overhead is only 3.3%. Transport Overhead Insertion (Serial Link) The TOH serial links are used to insert TOH bytes into the transmit data. The transmit TOH data and TOH_CLK_EN get retimed by TOH_CLK in order to meet setup and hold specifications of the device. The retimed TOH data is shifted into a 288-bit (36-byte by 8-bit) shift register and then multiplexed as an 8-bit bus to be inserted into the byte-wide data stream. Insertion from these serial links or pass-through of TOH from the byte-wide data is under software control. Transport Overhead Byte Ordering (FPGA to Backplane) In the transparent mode, SPE and TOH data received on parallel input bus is transferred, unaltered, to the serial LVDS output. However, B1 byte of STS#1 is always replaced with a new calculated value (the 11 bytes following B1 are replaced with all zeros). Also, A1 and A2 bytes of all STS-1s are always regenerated. TOH serial port in not used in the transparent mode of operation. In the TOH insert mode, SPE bytes are transferred, unaltered, from the input parallel bus to the serial LVDS output. On the other hand, TOH bytes are received from the serial input port and are inserted in the STS12 frame before being sent to the LVDS output. Although all TOH bytes from the 12 STS-1s are transferred into the device from each serial port, not all of them get inserted in the frame. There are three hardcoded exceptions to the TOH byte insertion:
s
In addition to the above hard-coded exceptions, the source of some TOH bytes can be further controlled by software. When configured to be in pass-through mode, the specific bytes must flow transparently from the parallel input. Note that blocks of 12 STS-1 bytes forming an STS-12 are controlled as a whole. There are 15 software controls per channel, as listed below:
s
Source of K1 and K2 bytes of the 12 STS-1s (24 bytes) is specified by a control bit (per channel control). Source of S1 and M0 bytes of the 12 STS-1s (24 bytes) is specified by a control bit (per channel control). Source of E1, F1, E2 bytes of the STS-1s (36 bytes) is specified by a control it (per channel control). Source of D1 bytes of the STS-1s (12 bytes) is specified by a control bit (per channel control). Source of D2 bytes of the 12 STS-1s (12 bytes) is specified by a control bit (per channel control). Source of D3 bytes of the 12 STS-1s (12 bytes) is specified by a control bit (per channel control). Source of D4 bytes of the 12 STS-1s (12 bytes) is specified by a control bit (per channel control). Source of D5 bytes of the 12 STS-1s (12 bytes) is specified by a control bit (per channel control). Source of D6 bytes of the 12 STS-1s (12 bytes) is specified by a control bit (per channel control). Source of D7 bytes of the 12 STS-1s (12 bytes) is specified by a control bit (per channel control). Source of D8 bytes of the 12 STS-1s (12 bytes) is specified by a control bit (per channel control). Source of D9 bytes of the 12 STS-1s (12 bytes) is specified by a control bit (per channel control). Source of D10 bytes of the 12 STS-1s (12 bytes) is specified by a control bit (per channel control). Source of D11 bytes of the 12 STS-1s (12 bytes) is specified by a control bit (per channel control). Source of D12 bytes of the 12 STS-1s (12 bytes) is specified by a control bit (per channel control).
s
s
s
s
s
s
s
s
s
s
s
s
s
Framing bytes (A1/A2 of all STS-1s) are not inserted from the serial input bus. Instead, they can always be regenerated. Parity byte (B1 of STS#1) is not inserted from the serial input bus. Instead, it is always recalculated (the 11 bytes following B1 are replaced with all zeros).
s
s
TOH reconstruction is dependent on the transmitter mode of operation. In the transparent mode of operation, TOH bytes on LVDS output are as shown in Table 3.
Pointer bytes (H1/H2/H3 of all STS-1s) are not inserted from the serial input bus. Instead, they always flow transparently from parallel input to LVDS output. 16
s
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Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description (continued)
Table 3. Transmitter TOH on LVDS Output (Transparent Mode)
A1 B1 A1 0 A1 0 A1 0 A1 0 A1 0 A1 0 A1 0 A1 0 A1 0 A1 0 A1 0 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2
Regenerated bytes. Transparent bytes from parallel input port.
In the TOH Insert mode of operation, TOH bytes on LVDS output are shown in the following Table. This also shows the order in which data is transferred to the serial TOH interface, starting with the must significant bit of the first A1 byte. The first bit of the first byte is replaced by an even parity check bit over all TOH bytes from the previous TOH frame. Table 4. Transmitter TOH on LVDS Output (TOH Insert Mode)
A1 B1 D1 H1 D4 D7
D10
A1 0 D1 H1 D4 D7
D10
A1 0 D1 H1 D4 D7
D10
A1 0 D1 H1 D4 D7
D10
A1 0 D1 H1 D4 D7
D10
A1 0 D1 H1 D4 D7
D10
A1 0 D1 H1 D4 D7
D10
A1 0 D1 H1 D4 D7
D10
A1 0 D1 H1 D4 D7
D10
A1 0 D1 H1 D4 D7
D10
A1 0 D1 H1 D4 D7
D10
A1 0 D1 H1 D4 D7
D10
A2 E1 D2 H2 K1 D5 D8
D11
A2 E1 D2 H2 K1 D5 D8
D11
A2 E1 D2 H2 K1 D5 D8
D11
A2 E1 D2 H2 K1 D5 D8
D11
A2 E1 D2 H2 K1 D5 D8
D11
A2 E1 D2 H2 K1 D5 D8
D11
A2 E1 D2 H2 K1 D5 D8
D11
A2 E1 D2 H2 K1 D5 D8
D11
A2 E1 D2 H2 K1 D5 D8
D11
A2 E1 D2 H2 K1 D5 D8
D11
A2 E1 D2 H2 K1 D5 D8
D11
A2 E1 D2 H2 K1 D5 D8
D11
F1 D3 H3 K2 D6 D9
D12
F1 D3 H3 K2 D6 D9
D12
F1 D3 H3 K2 D6 D9
D12
F1 D3 H3 K2 D6 D9
D12
F1 D3 H3 K2 D6 D9
D12
F1 D3 H3 K2 D6 D9
D12
F1 D3 H3 K2 D6 D9
D12
F1 D3 H3 K2 D6 D9
D12
F1 D3 H3 K2 D6 D9
D12
F1 D3 H3 K2 D6 D9
D12
F1 D3 H3 K2 D6 D9
D12
F1 D3 H3 K2 D6 D9
D12
S1
S1
S1
S1
S1
S1
S1
S1
S1
S1
S1
S1
M0
M0
M0
M0
M0
M0
M0
M0
M0
M0
M0
M0
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
Regenerated bytes. Inserted or transparent bytes. Blocks of 12 STS-1 bytes are controlled as a whole. There are 15 controls/channel: K1/K2, S1/M0, E1/F1/E2, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12. Transparent bytes (from parallel input port). Inserted bytes from TOH serial input port.
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Backplane Transceiver Core Detailed Description (continued)
A1/A2 Frame Insert and Testing The A1 and A2 bytes provide a special framing pattern that indicates where a STS-1 begins in a bit stream. All 12 A1 bytes of each STS-12 are set to 0xF6, and all 12 A2 bytes of the STS-12 are set to 0x28 when not overridden with an user-specified value for testing. A1/A2 testing (corruption) is controlled per stream by the A1/A2 error insert register. When A1/A2 corruption detection is set for a particular stream, the A1/A2 values in the corrupted A1/A2 value registers are sent for the number of frames defined in the corrupted A1/A2 frame count register. When the corrupted A1/A2 frame count register is set to zero, A1/A2 corruption will continue until the A1/A2 error insert register is cleared. On a per-device basis, the A1 and A2 byte values are set, as well as the number of frames of corruption. Then, to insert the specified A1/A2 values, each channel has an enable register. When the enable register is set, the A1/A2 values are corrupted for the number specified in the number of frames to corrupt. To insert errors again, the per-channel fault insert register must be cleared, and set again. Only the last A1 and the first A2 are corrupted. B1 Calculation and Insertion A bit interleaved parity -8 (BIP-8) error check set for even parity over all the bits of an STS-1 frame. B1 is defined for the first STS-1 in an STS-N only. The B1 calculation block computes a BIP-8 code, using even parity over all bits of the previous STS-12 frame after scrambling and is inserted in the B1 byte of the current STS-12 frame before scrambling. Per-bit B1 corruption is controlled by the force BIP-8 corruption register (register address 0F). For any bit set in this register, the corresponding bit in the calculated BIP-8 is inverted before insertion into the B1 byte position. Each stream has an independent fault insert register that enables the inversion of the B1 bytes. B1 bytes in all other STS1s in the stream are filled with zeros.
Stream Disable When disabled via the appropriate bit in the stream enable register, the prescrambled data for a stream is set to all ones, feeding the HSI. The HSI macro is powered down on a per-stream basis, as are its LVDS outputs. Scrambler The data stream is scrambled using a frame synchronous scrambler of sequence length 127. The scrambling function can be disabled by software. The generating polynomial for the scrambler is 1 + x 6 + x7. This polynomial conforms to the standard SONET STS-12 data format. The scrambler is reset to 1111111 on the first byte of the SPE (byte following the Z0 byte in the twelfth STS-1). That byte and all subsequent bytes to be scrambled are exclusive-ORed, with the output from the byte-wise scrambler. The scrambler runs continuously from that byte on throughout the remainder of the frame. A1, A2, J0, and Z0 bytes are not scrambled. System Frame Pulse and Line Frame Pulse System frame pulse (for transmitter) and line frame pulse (for receiver) are generated in FPGA logic. A1/A2 framing is used on the link for locating the 8 kHz frame location. All frames sent to the FPGA are aligned to the FPGA frame pulse LINE_FP which is provided by the FPGA to the STM macro. All frames sent from the FPGA to the STM will be aligned to the frame pulse SYS_FP that is supplied to the STM macro. In either directions, system frame pulse and line frame pulse are active for one system clock cycle, indicating the location of A1 byte of STS#1. They are common to all four channels.
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
The B1 calculation block computes a BIP-8 (Bit Interleaved Parity 8-bits) code, using even parity over all bits of the previous STS-12 frame before descrambling; this value is checked against the B1 byte of the current frame after descrambling. A per-stream B1 error counter is incremented for each bit that is in error. The error counter may be read via the CPU interface. Descrambling. The streams are descrambled using a frame synchronous descrambler of sequence length 127 with a generating polynomial of 1 + x6 + x7. The A1/A2 framing bytes, the section trace byte (J0) and the growth bytes (Z0) are not descrambled. The descrambling function can be disabled by software. AIS-L Insertion. Alarm indication signal (AIS) is a continuous stream of unframed 1s sent to alert downstream equipment that the near-end terminal has failed, lost its signal source, or has been temporarily taken out of service. If enabled in the AIS_L force register, AIS-L is inserted into the received frame by writing all ones for all bytes of the descrambled stream. AIS-L Insertion on Out-of-Frame. If enabled via a register, AIS-L is inserted into the received frame by writing all ones for all bytes of the descrambled stream when the framer indicates that an out-of-frame condition exists. Internal Parity Generation Even parity is generated on all data bytes and is routed in parallel with the data to be checked before the protection switch MUX at the parallel output. FIFO Alignment (Backplane -> FPGA) The alignment FIFO allows the transfer of all data to the system clock. The FIFO sync block (Figure 5) allows the system to be configured to allow the frame alignment of multiple slightly varying data streams. This optional alignment ensures that matching STS-12 streams will arrive at the FPGA end in perfect data sync. The frame alignment is configurable to allow for the possibility of fully independent (i.e., total frame misalignment) STS-12s.
Backplane Transceiver Core Detailed Description (continued)
STM Receiver (Backplane -> FPGA)
The ORT4622 has four receiving channels that can be treated as one STS-48 stream, or treated as independent channels. Incoming data is received through LVDS serial ports at the data rate of 622 Mbits/s. The receiver can handle the data streams with frame offsets of up to 12 bytes which would be due to timing skews between cards and along backplane traces. The received data streams are processed in the HSI and the STM, and then passed through the CIC boundary to the FPGA logic. Framer Block The framer block, in Figure 5, takes byte-wide data from the HSI, and outputs a byte-aligned, byte-wide data stream and 8 kHz sync pulse. The framer algorithm determines the out-of-frame/in-frame status of the incoming data and will cause interrupts on both an errored frame and an out-of-frame (OOF) state. The framer detects the A1/A2 framing pattern and generates the 8 kHz frame pulse. When the framer detects OOF, it will generate an interrupt. Also, the framer detects an errored frame and increments an A1/A2 frame error counter. The counter can be monitored by a processor to compile performance status on the quality of the backplane. Because the ORT4622 is intended for use between it and another ORT4622 or other devices via a backplane, there is only one errored frame state. Thus after two transitions are missed, the state machine goes into the OOF state and there is no severely errored frame (SEF) or loss-of-frame (LOF) indication. B1 Calculate and Descramble (Backplane -> FPGA) Each Rx block receives byte-wide scrambled 77.76 MHz data and a frame sync from the framer. Since each HSI is independently clocked, the Rx block operates on individual streams. Timing signals required to locate overhead bytes to be extracted are generated internally based on the frame sync. The Rx block produces byte-wide (optionally) descrambled data and an output frame sync for the alignment FIFO block.
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Backplane Transceiver Core Detailed Description (continued)
alignment. The read control block is synched only once on start-up; any further synchronization is software controlled. The action of resynching a read control block will always cause loss of data. A register allows the read control block to be resynched. Link Alignment. The general operation of the link alignment algorithm is to wait 12 clocks (i.e., half the FIFO) from the arriving frame pulse and then signal the read control block to begin reading. For perfectly aligned frame pulses across the links, it is simply a matter of counting down 12 and then signaling the read control block. The algorithm down counts by one until all of the frame pulses have arrived and then by two when they are all present. For example (Figure 7), if all pulses arrive together, then alignment algorithm would count 24 (12 clocks); if, however, the arriving pulses are spread out over four clocks, then it would count one for the first four pulses and then two per clock afterward, which gives a total of 14 clocks between first frame pulse and the first read. This puts the center of arriving frame pulses at the halfway point in the buffer. This is the extent of the algorithm, and it has no facility for actively correcting problems once they occur. The write control block receives byte-wide data at 77.76 MHz and a frame pulse two clocks before the first A1 byte of the STS-12 frame. It generates the write address for the FIFO block. The first A1 in every STS12 stream is written in the same location (address 0) in the FIFO. Also, a frame bit is passed through the FIFO along with the first byte before the first A1 of the STS12. The read control block synchronizes the reading of the FIFO for streams that are to be aligned. Reading begins when the FIFO sync signals that all of the applicable A1s and the appropriate margin have been written to the FIFO. All of the read blocks to be synchronized begin reading at the same time and same location in memory (address 0). The alignment algorithm takes the difference between read address and write address to indicate the relative clock alignments between STS-12 streams. If this depth indication exceeds certain limits (12 clocks), then an interrupt is given to the microprocessor (alignment overflow). Each STS-12 stream can be realigned by software if it gets too far out of line (this would cause a loss of data). For background applications that have less than 154.3 ns of interlink skew, misalignment will not occur.
STS-12 STREAM A STS-12 STREAM B FIFO SYNC STS-12 STREAM C STS-12 STREAM D
5-8577 (F)
Figure 5. Interconnect of Streams for FIFO Alignment The incoming data from the clock and data recovery can be separated into four STS-12 channels (A, B, C, and D). These streams can be frame aligned in the patterns shown in Figure 6.
STREAM A STREAM B STREAM C STREAM D
STREAM A STREAM B STREAM C STREAM D
5-8575 (F)
Figure 6. Alignment of Four STS-12 Streams There is also a provision to allow certain streams to be disabled (i.e., not producing interrupts or affecting synchronization). These streams can be enabled at a later time without disrupting other streams. The FIFO block consists of a 24 by 10-bit FIFO per link. This FIFO is used to align up to 154.3 ns of interlink skew and to transfer to the system clock. The FIFO sync circuit takes metastable hardened frame pulses from the write control blocks and produces sync signals that indicate when the read control blocks should begin reading from the first FIFO location. On top of the sync signals, this block produces an error indicator which indicates that the signals to be aligned are too far apart for alignment (i.e., greater than 18 clocks apart). Sync and error signals are sent to read control block for
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Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description (continued)
12 CLOCKS LAST FP ARRIVES ALL FPs ARRIVE TOGETHER (WRITING BEGINS) 24-byte FIFO SYNC. PULSE (READING BEGINS) 4 CLOCKS FIRST FP ARRIVES (WRITING BEGINS) PERFECTLY ALIGNED FRAMES 4-byte SPREAD IN ARRIVING FRAMES 24-byte FIFO SYNC. PULSE (READING BEGINS) 10 CLOCKS
5-8584 (F)
Figure 7. Examples of Link Alignment Pointer Mover Block (Backplane -> FPGA) The pointer mover maps incoming frames to the line framing that is supplied by the FPGA logic. The K1/K2 bytes and H1-SS bits are also passed through to the pointer generator so that the FPGA can receive them. The pointer mover handles both concatenations inside the STS-12, and to other STS-12s inside the core. The pointer mover block can correctly process any length of concatenation of STS frames (multiple of three) as long as it begins on an STS-3 boundary (i.e., STS-1 number one, four, seven, ten, etc.) and is contained within the smaller of STS-3, 12, or 48. See details in Table 5. Table 5. Valid Starting Positions for an STS-Mc STS-1 Number 1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 STS-3cSPE YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES STS-6cSPE YES YES YES NO YES YES YES NO YES YES YES NO YES YES YES NO STS-9cSPE YES YES NO NO YES YES NO NO YES YES NO NO YES YES NO NO STS-12cSPE YES NO NO NO YES NO NO NO YES NO NO NO YES NO NO NO STS-15cSPE YES YES YES YES YES YES YES YES YES YES YES YES NO NO NO NO STS-18c to STS-48c SPEs YES -- -- -- -- -- -- -- -- -- -- NO NO NO NO NO
Note: YES = STS-Mc SPE can start in that STS-1. NO = STS-Mc SPE cannot start in that STS-1. -- = YES or NO, depending on the particular value of M.
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Backplane Transceiver Core Detailed Description (continued)
NORM
Pointer Interpreter State Machine. The pointer interpreter's highest priority is to maintain accurate data flow (i.e., valid SPE only) into the elastic store. This will ensure that any errors in the pointer value will be corrected by a standard, fully SONET compliant, pointer interpreter without any data hits. This means that error checking for increment, decrement, and new data flag (NDF) (i.e., eight of 10) is maintained in order to ensure accurate data flow. A single valid pointer (i.e., 0--782) that differs from the current pointer will be ignored. Two consecutive incoming valid pointers that differ from the current pointer will cause a reset of the J1 location to the latest pointer value (the generator will then produce an NDF). This block is designed to handle single bit errors without affecting data flow or changing state. The pointer interpreter has only three states (NORM, AIS, and CONC). NORM state will begin whenever two consecutive NORM pointers are received. If two consecutive NORM pointers are received that both differ from the current offset, then the current offset will be reset to the last received NORM pointer. When the pointer interpreter changes its offset, it causes the pointer generator to receive a J1 value in a new position. When the pointer generator gets an unexpected J1, it resets its offset value to the new location and declares an NDF. The interpreter is only looking for two consecutive pointers that are different from the current value. These two consecutive NORM pointers do not have to have the same value. For example, if the current pointer is ten and a NORM pointer with offset of 15 and a second NORM pointer with offset of 25 are received, then the interpreter will change the current pointer to 25. The receipt of two consecutive CONC pointers causes CONC state to be entered. Once in this state, offset values from the head of the concatenation chain are used to determine the location of the STS SPE for each STS in the chain. Two consecutive AIS pointers cause the AIS state to occur. Any two consecutive normal or concatenation pointers will end this AIS state. This state will cause the data leaving the pointer generator to be overwritten with 0xFF.
2
C
xN
ON
OR
xC
M
2
OR
M
xA
2
xN
IS
2
2 x CONC CONC 2 x AIS AIS
5-8589 (F)
Figure 8. Pointer Mover State Machine Pointer Generator. The pointer generator maps the corresponding bytes into their appropriate location in the outgoing byte stream. The generator also creates offset pointers based on the location of the J1 byte as indicated by the pointer interpreter. The generator will signal NDFs when the interpreter signals that it is coming out of AIS state. The pointer generator resets the pointer value and generates NDF every time a byte marked J1 is read from the elastic store that doesn't match the previous offset. Increment and decrement signals from the pointer interpreter are latched once per frame on either the F1 or E2 byte times (depending on collisions); this ensures constant values during the H1 through H3 times. The choice of which byte time to do the latching on is made once when the relative frame phases (i.e., received and system) are determined. This latch point is then stable unless the relative framing changes and the received H byte times collide with the system F1 or E2 times, in which case the latch point would be switched to the collision-free byte time. There is no restriction on how many or how often increments and decrements are processed. Any received increment or decrement is immediately passed to the generator for implementation regardless of when the last pointer adjustment was made. The responsibility for meeting the SONET criteria for maximum frequency of pointer adjustments is left to an upstream pointer processor. When the interpreter signals an AIS state, the generator will immediately begin sending out 0xFF in place of data and H1, H2, H3. This will continue until the interpreter returns to NORM or CONC (pointer mover state machine) states and a J1 byte is received.
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Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
bytes of each channel through one of four corresponding serial ports. The four TOH serial ports are synchronized to the TOH clock (the same clock that is being used by the serial ports on the transmitter side). This free-running TOH clock is provided to the core by external circuitry and operates at a minimum frequency of 25 MHz and a maximum frequency of 77.76 MHz. Data is transferred over serial links in a bursty fashion as controlled by the Rx TOH clock enable signal, which is generated by the ASIC and common to the four channels. All TOH bytes of STS-12 streams are transferred over the appropriate serial link in the same order in which they appear in a standard STS-12 frame. Data transfer should be preformed on a row-by-row basis such that internal data buffering needs is kept to a minimum. Data transfers on the serial links will be synchronized relative to the Rx TOH frame signal. Receiver TOH Reconstruction
Backplane Transceiver Core Detailed Description (continued)
Transport Overhead Extraction Transport overhead is extracted from the receive data stream by the TOH extract block. The incoming data gets loaded into a 36-byte shift register on the system clock domain. This, in turn, is clocked onto the TOH clock domain at the start of the SPE time, where it can be clocked out. During the SPE time, the receiver TOH frame pulse is generated, RX_TOH_FP, which indicates the start of the row of 36 TOH bytes. This pulse, along with the receive TOH clock enable, RX_TOH_CK_EN, as well as the TOH data, are all launched on the rising edge of the TOH clock TOH_CLK. TOH Byte Ordering (Backplane to FPGA) The TOH processor is responsible for dropping all TOH Table 6. Receiver TOH (Output Parallel Bus)
A1 0 0 H1 0 0 0 0 0 A1 0 0 H1 0 0 0 0 0 A1 0 0 H1 0 0 0 0 0 A1 0 0 H1 0 0 0 0 0 A1 0 0 H1 0 0 0 0 0 A1 0 0 H1 0 0 0 0 0 A1 0 0 H1 0 0 0 0 0 A1 0 0 H1 0 0 0 0 0 A1 0 0 H1 0 0 0 0 0 A1 0 0 H1 0 0 0 0 0 A1 0 0 H1 0 0 0 0 0 A1 0 0 H1 0 0 0 0 0 A2 0 0 H2 K1 0 0 0 0 A2 0 0 H2 0 0 0 0 0 A2 0 0 H2 0 0 0 0 0 A2 0 0 H2 0 0 0 0 0 A2 0 0 H2 0 0 0 0 0 A2 0 0 H2 0 0 0 0 0
Receiver TOH reconstruction on output parallel bus is as shown in the following table.
A2 0 0 H2 0 0 0 0 0
A2 0 0 H2 0 0 0 0 0
A2 0 0 H2 0 0 0 0 0
A2 0 0 H2 0 0 0 0 0
A2 0 0 H2 0 0 0 0 0
A2 0 0 H2 0 0 0 0 0
0 0 0 H3 K2 0 0 0 0
0 0 0 H3 0 0 0 0 0
0 0 0 H3 0 0 0 0 0
0 0 0 H3 0 0 0 0 0
0 0 0 H3 0 0 0 0 0
0 0 0 H3 0 0 0 0 0
0 0 0 H3 0 0 0 0 0
0 0 0 H3 0 0 0 0 0
0 0 0 H3 0 0 0 0 0
0 0 0 H3 0 0 0 0 0
0 0 0 H3 0 0 0 0 0
0 0 0 H3 0 0 0 0 0
Regenerated bytes. Regenerated bytes (under pointer generator control-SS bits must be transparent-AIS-P must be supported). Bytes taken from Elastic Store Buffer, on negative stuff opportunity-else, forced to all zeros. Transparent or all zeros (K1/K2 are either taken from K1/K2 buffer or forced to all zeros-soft, control). In transparent mode, AIS-L must be supported. All zero bytes.
On the TOH serial port, all TOH bytes are dropped as received on the LVDS input (MSB first). The only exception is the most significant bit of byte A1 of STS#1, which is replaced with an even parity bit. This parity bit is calculated over the previous TOH frame. Also, on AIS-L (either resulting from LOF or forced through software), all TOH bits are forced to all ones with proper parity (parity we automatically ends up being set to 1 on AIS-L). Special TOH Byte Functions K1 and K2 Handling. The K1 and K2 bytes are used in automatic protection switch (APS) applications. K1 and K2 bytes can be optionally passed through the pointer mover under software control, or can be set to zero with the other TOH bytes. A1 and A2 Handling. As discussed previously, the A1 and A2 bytes are used for a framing header. A1 and A2 bytes are always regenerated and set to hexadecimal F6 and 28, respectively.
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Backplane Transceiver Core Detailed Description (continued)
SPE and C1J1 Outputs. These two signals for each channel are passed to the FPGA logic to allow a pointer processor or other function to extract payload without interpreting the pointers. For the ORT4622, each frame has 12 STS-1s. In the SPE region, there are 12 J1 pulses for each STS-1s. There is one C1(J0, new SONET specifications use J0 instead of C1 as section trace to identify each STS-1 in an STS-N) pulse in the TOH area for one frame. Thus, there is a total of 12 J1 pulses and one C1(J0) pulse per frame. C1(J0) pulse is coincident with the J0 of STS1 #1. In each frame, the SPE flag is active when the data stream is in SPE area. SPE behavior is dependent on pointer movement and concatenation. Note that in the TOH area, H3 can also carry valid data. When valid SPE data is carried in this H3 slot, SPE is high in this particular TOH time slot. In the SPE region, if there is no valid data during any SPE column, the SPE signal will be set to low. SPE allow a pointer processor to extract payload without interpreting the pointers. The SPE and C1J1 functionality are described in Table 7. For generic data operation, valid data is available when SPE is 1 and the C1J1 signal is ignored. Table 7. SPE and C1J1 Functionality SPE 0 0 C1J1 0 1 Description TOH information excluding C1(J0) of STS1 #1. Position of C1(J0) of STS1 #1 (one per frame). Typically used to provide a unique link identification (256 possible unique links) to help ensure cards are connected into the backplane correctly or cables are connected correctly. SPE information excluding the 12 J1 bytes. Position of the 12 J1 bytes.
1 1
0 1
Note: The following rules are observed for generating SPE and C1J1 signals: on occurrence of AIS-P on any of the STS-1, there is no corresponding J1 pulse. In case of concatenated payloads (up to STS48c), only the head STS-1 of the group has an associated J1 pulse. C1J1 signal tracks any pointer movements. During a negative justification event, SPE is set high during the H3 byte to indicate that payload data is available. During a positive justification event, SPE is set low during the positive stuff opportunity byte to indicate that payload data is not available.
STS-12
TOH ROW # 1
SPE ROW # 1
1ST SPE BYTES OF THE 12 STS-1S
A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 J0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 1 2 3 4 5 6 7 8 9 10 11 12
STS-12
SPE C1 PULSE C1J1 J1 PULSE OF 3RD STS-1
5-9330(F)
Notes: C1J1 signal behavior shown in this figure is just for illustration purposes: C1 pulse position must always be as shown; however, position of J1 pulses vary based on path overhead location of each STS-1 within the STS-12 stream. C1J1 signal must always be active during C1(J0) time slot of STS#1. C1J1 signal must also be active during the twelve J1 time slots. However, C1J1 must not be active for any STS-1 for which AIS-P is generated. Also, on concatenated payloads, only the head of the group must have a J1 pulse.
Figure 9. SPE and C1J1 Functionality 24 Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description (continued)
STS-12
TOH ROW # 4
SPE ROW # 4
NEGATIVE STUFF OPPORTUNITY BYTES
POSITIVE STUFF OPPORTUNITY BYTES
H1 H1 H1 H1 H1 H1 H1 H1 H1 H1 H1 H1 H2 H2 H2 H2 H2 H2 H2 H2 H2 H2 H2 H2 H3 H3 H3 H3 H3 H3 H3 H3 H3 H3 H3 H3 1 2 3 4 5 6 7 8 9 10 11 12
STS-12
SPE SIGNAL SHOWS NEGATIVE STUFFING FOR 2ND STS-1, AND POSITIVE STUFFING FOR 6TH STS-1
SPE
5-9331
Notes: SPE signal behavior shown in this figure is just for illustration purposes: SPE behavior is dependent on pointer movements and concatenation. SPE signal must be high during negative stuff opportunity byte time slots (H3) for which valid data is carried (negative stuffing). SPE signal must be low during positive stuff opportunity byte time slots for which there is no valid data (positive stuffing).
Figure 10. SPE Stuff Bytes
Powerdown Mode
Powerdown mode will be entered when the corresponding channel is disabled. Channels can be independently enabled or disabled under software control. Parallel data bus output enable and TOH serial data output enable signals are made available to the FPGA logic. The HSI macrocell's corresponding channel is also powered down. The device will power up with all four channels in powerdown mode. In addition, an LVDS_EN pin has been added to control the LVDS pins during boundary scan. During functional operation, enabling/disabling LVDS buffers is controlled by software registers. When in boundary scan mode, LVDS_EN controls the enabling/disabling of LVDS buffers instead of software registers. This LVDS_EN pin should be pulled high on the board for functional operation, and pulled low during boundary scan.
In STS-12 mode, the channel A receive data bus port is used for both channel A and channel B. Similarly, the channel C receive data bus port is used for both channel C and channel D. Channel B and channel D become the redundant channels. The channel B and channel D receive data bus ports are unused. Soft registers provide independent control to the protection switching MUXes for both parallel data ports and serial TOH data ports. When direct hardware control for protection switching is needed, external protection switch pins are available for channels A and B, and also channels C and D. The external protection switch pins only support parallel SPE/TOH data protection switching, but not the serial TOH data. In STS-48 mode, two independent devices are required to work and protect for redundancy. Parallel and serial port output pins on the FPGA side should be 3-stated as the basis for supporting redundancy. The existing local bus enable signals at the CIC can be used as 3-state controls for FPGA data bus if needed, which can be easily accessed by software control. Users can also create their own protection switch 3state enable signals either in FPGA logic or external to the device, depending on the specific application.
Redundancy and Protection Switching
The ORT4622 supports STS-12/STS-48 redundancy by either software or hardware control for protection switching applications. For the transmitter mode, no additional functionality is required for redundant operation. For receiving data, STS-12 data redundancy can be implemented within the same device, while STS-48 and above data stream requires a pair of ORT4622 devices to support redundancy. Lucent Technologies Inc. Lucent Technologies Inc.
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Memory Map
Definition of Register Types
There are six structural register elements: sreg, creg, preg, iareg, isreg, and iereg. There are no mixed registers in the chip. This means that all bits of a particular register (particular address) are structurally the same. Table 8. Structural Register Elements Element sreg Register Description
creg
preg
iareg
isreg
ereg
Status Register A status register is read only, and, as the name implies, is used to convey the status information of a particular element or function of the ORT4622 core. The reset value of an sreg is really the reset value of the particular element or function that is being read. In some cases, an sreg is really a fixed value. An example of which is the fixed ID and revision registers. Control Register A control register is read and writable memory element inside core control. The value of a creg will always be the value written to it. Events inside the ORT4622 core cannot effect creg value. The only exception is a soft reset, in which case the creg will return to its default value. The control register have default values as defined in the default value column of Table 9. Pulse Register Each element, or bit, of a pulse register is a control or event signal that is asserted and then deasserted when a value of one is written to it. This means that each bit is always of value 0 until it is written to, upon which it is pulsed to the value of one and then returned to a value of 0. A pulse register will always have a read value of 0. Interrupt Alarm Each bit of an interrupt alarm register is an event latch. When a particular event is Register produced in the ORT4622 core, its occurrence is latched by its associated iareg bit. To clear a particular iareg bit, a value of one must be written to it. In the ORT4622 core, all isreg reset values are 0. Interrupt Status Each bit of an interrupt status register is physically the logical-OR function. It is a Register consolidation of lower level interrupt alarms and/or isreg bits from other registers. A direct result of the fact that each bit of the isreg is a logical-OR function means that it will have a read value of one if any of the consolidation signals are of value one, and will be of value 0 if and only if all consolidation signals are of value 0. In the ORT4622 core, all isreg default values are 0. Interrupt Enable Each bit of a status register or alarm register has an associated enable bit. If this bit Register is set to value one, then the event is allowed to propagate to the next higher level of consolidation. If this bit is set to zero, then the associated iareg or isreg bit can still be asserted but an alarm will not propagate to the next higher level. An interrupt enable bit is an interrupt mask bit when it is set to value 0.
Registers Access and General Description The memory map comprises three address blocks:
s s s
Generic register block: ID, revision, scratch pad, lock, FIFO alignment, and reset registers. Device register block: control and status bits, common to the four channels. Channel register blocks: each of the four channels have an address block. The four address blocks have the exact same structure with a constant address offset between channel register blocks.
All registers are write-protected by the lock register, except for the scratch pad register. The lock register is a 16-bit read/write register. Write access is given to registers only when the key value 0xA001 is present in the lock register. An error flag will be set upon detecting a write access when write permission is denied. The default value is 0x0000. After powerup reset or soft reset, unused register bits will be read as zeros. Unused address locations are also read as zeros. Write only register bits will be read as zeros. The detailed information on register access and function are described on the tables, memory map, and memory map bit description. 26 Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Memory Map (continued)
Memory Map Overview
Table 9. Memory Map
ADDR [6:0] Reg. Type DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Default Value Notes (hex)
Generic Register Block
00 01 02 03 04 05 06 sreg sreg sreg creg creg creg preg fixed rev [7:0] fixed ID LSB [7:0] fixed ID MSB [7:0] scratch pad [7:0] lockreg MSB [7:0] lockreg LSB [7:0] -- -- 01 01 A0 00 00 00 NA 1
--
--
--
--
FIFO align- global ment comreset mand command LVDS lpbk control
Device Register Block 08 creg --
--
--
09
creg
--
--
--
0a 0b 0c
creg creg creg
-- -- --
0d 0e 0f
creg creg creg
-- -- -- -- scrambler/ input/ descramoutput bler parallel control bus parity control A1 error insert value [7:0] A2 error insert value [7:0] transmitter B1 error insert mask [7:0]
parallel parallel serial port serial port port out- port outoutput output put MUX put MUX MUX MUX select for select for select for select for ch C ch A ch C ch A FIFO aligner threshold value (min) [4:0] FIFO aligner threshold value (max) [4:0] line loopnumber of consecutive A1/A2 errors to back generate [3:0] control
Rx TOH frame and Rx TOH clock enable control --
ext prot sw en
ext prot STS-48 sw STS-12 sel function (unused in ORT4622)
00
2
0F
02 15 60
3
00 00 00
Notes: 1.Generic register block. 2.Device register block-Rx. 3.Device register block-Tx.
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Memory Map (continued)
Table 9. Memory Map
ADDR [6:0] Reg. Type DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Default Value Notes (hex) 00 00 00 4
Device Register Block (continued) 10 isreg -- -- 11 12 iereg iareg -- -- -- --
-- -- --
13
iereg
--
--
--
per ch D ch C ch B ch A device int interrupt interrupt interrupt interrupt enable/mask register [4:0] -- -- -- write to frame locked offset register error flag error flag -- -- -- enable/mask register [1:0] TOH force ais-l Rx serial control behavior output in LOF port par err ins cmd
00
Channel Register Block 20, 38, creg channel parallel Rx K1/K2 ProtecProtec50, 68 tion enable/ output source tion * switching switching disable bus parity select 3-state control err ins 3-state control of control of cmd TOH data parallel output data output 21, 39, creg Tx mode Tx E1 F1 Tx S1 M0 Tx K1/K2 Tx D12 51, 69 of opera- E2 source source source source tion select select select select 22, 3a, creg Tx D8 Tx D7 Tx D6 Tx D5 Tx D4 52, 6a source source source source source select select select select select 23, 3b, creg -- -- -- -- --
53, 6b 24, 3c, 54, 6c 25, 3d, 55, 6d
01
5
Tx D11 source select Tx D3 source select --
sreg
sreg
Concatindication 12 Concatin- Concatin- Concatin- Concatin- Concatindication dication dication dication dication 11 8 5 2 10
--
--
--
--
Concatindication 9 Concatindication 7
Tx D10 source select Tx D2 source select B1 error insert command Concatindication 6 Concatindication 4
Tx D9 source select Tx D1 source select A1/A2 error ins command Concatindication 3 Concatindication 1
00
6
00
00
NA
7
NA
Notes: 1.Generic register block. 2.Device register block-Rx. 3.Device register block-Tx. 4.Top-level interrupts. 5.Rx control. 6.Tx control signals. 7.Per STS#1 cos flag. * ADDR values delimited by a comma indicate the address for each of four channels, from channel A to D. For example, the register to Tx control signals has addresses of 20, 38, 50, and 68. This indicates that channel A Tx control signals are at address 20, control B Tx control signals are at address
28
Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Memory Map (continued)
Table 9. Memory Map
ADDR [6:0] Reg. Type DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Default Value Notes (hex) 00 8
Channel Register Block (continued) 26, 3e, isreg -- --
56, 6e
--
--
--
27, 3f, 57, 6f 28, 40, 58, 70
iereg iareg
-- --
-- --
--
--
--
elastic ais-p flag per store STS-12 overflow alarm flag flag enable/mask register [2:0]
00 00 9
29,41, 59, 71 2a, 42, 5a, 72 2b, 43, 5b, 73 2c, 44, 5c, 74
iereg iareg
-- --
-- --
TOH input LVDS link LOF flag Receiver FIFO serial parallel B1 parity internal aligner input port bus error flag path threshold parity parity parity error flag error flag error flag error flag enable/mask register [5:0] -- -- AIS interrupt flag 9 AIS interrupt flag 7 enable/ mask AIS interrupt flag 9 enable/ mask AIS interrupt flag 7 ES overflow flag 9 AIS AIS interrupt interrupt flag 6 flags 3 AIS AIS interrupt interrupt flag 4 flag 1 enable/ enable/ mask AIS mask AIS interrupt interrupt flag 6 flag 3 enable/ enable/ mask AIS mask AIS interrupt interrupt flag 4 flag 1 ES ES overflow overflow flag 6 flag 3
00 00 10
iareg
iereg
2d, 45, 5d, 75
iereg
2e, 46, 5e, 76
iareg
AIS interrupt flags 12 AIS AIS AIS AIS AIS interrupt interrupt interrupt interrupt interrupt flag 11 flag 8 flag 5 flag 2 flag 10 -- -- -- -- enable/ mask AIS interrupt flag 12 enable/ enable/ enable/ enable/ enable/ mask AIS mask AIS mask AIS mask AIS mask AIS interrupt interrupt interrupt interrupt interrupt flag 10 flag 11 flag 8 flag 5 flag 2 -- -- -- -- ES overflow flag 12
00
00
00
00
Notes: 1. Generic register block. 2. Device register block-Rx. 3. Device register block-Tx. 4. Top-level interrupts. 5. Rx control. 6. Tx control signals. 7. Per STS#1 cos flag. 8. Per channel interrupt. 9. Per STS-12 interrupt flags. 10. Per STS-1interrupt flags.
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Memory Map (continued)
Table 9. Memory Map
ADDR [6:0] Reg. Type DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Default Value Notes (hex) 00
Channel Register Block (continued) 2f, 47, iareg ES ES ES 5f, 77 overflow overflow overflow flag 11 flag 8 flag 5 30, 48, iereg -- -- --
60, 78
enable/ mask ES overflow flag 11 32, 4a, counter overflow
31, 49, 61, 79 62, 7a 33, 4b, counter overflow 63, 7b 34, 4c, counter overflow 64, 7c
Notes: 1. Generic register block. 2. Device register block-Rx. 3. Device register block-Tx. 4. Top-level interrupts. 5. Rx control. 6. Tx control signals. 7. Per STS#1 cos flag. 8. Per channel interrupt. 9. Per STS-12 interrupt flags. 10. Per STS-1interrupt flags. 11. Binning.
iereg
ES ES ES ES overflow overflow overflow overflow flag 10 flag 7 flag 4 flag 1 enable/ enable/ enable/ enable/ mask ES mask ES mask ES mask ES overflow overflow overflow overflow flags flag flags flags 12 9 6 3 enable/ enable/ enable/ enable/ enable/ enable/ enable/ mask ES mask ES mask ES mask ES mask ES mask ES mask ES overflow overflow overflow overflow overflow overflow overflow flag 10 flag 7 flag 4 flag 1 flag 8 flag 5 flag 2 LVDS link B1 parity error counter LOF counter A1/A2 frame error counter
ES overflow flag 2 --
10
00
00
00 00 00
11
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Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Memory Map (continued)
Table 10. Memory Map Bit Descriptions
Bit/Register Name(s) Bit/ Default Register Register Value Location Type (hex) (hex)
Description
Generic Register Block
fixed rev [7:0] fixed ID LSB [7:0] fixed ID MSB [7:0] scratch pad [7:0] lockreg MSB [7:0] lockreg LSB [7:0] 00 [7:0] 01 [7:0] 02 [7:0] 03 [7:0] 04 [7:0] 05 [7:0] sreg 01 01 A0 00 00 00 --
creg creg
FIFO alignment command global reset command
06 [0] 06 [1]
preg
NA
The scratch pad has no function and is not used anywhere in the ORT4622 core. However, this register can be written to and read from. In order to write to registers in memory locations 06 to 7F, lockreg MSB and lockreg LSB must be respectively set to the values of A0 and 01. If the MSB and LSB lockreg values are not set to {A0, 01}, then any values written to the registers in memory locations 06 to 7F will be ignored. After reset (both hard and soft), the ORT4622 core is in a write locked mode. The ORT4622 core needs to be unlocked before it can be written to. Also note that the scratch pad register (03) can always be written to since it is unaffected by write lock mode. The FIFO alignment and global reset commands are both accessed via the pulse register in memory address 06. The FIFO alignment command is used to frame align the outputs of the four receive stm stream FIFOs. The global reset command is a soft (software initiated) reset. Nevertheless, the global reset command will have the exact reset effect as a hard (RST_N pin) reset.
Device Register Block
LVDS loopback control STS48 STS12 sel ext prot sw en ext prot sw func 08 [0] 08 [1] 08 [3:2] creg creg creg 0 0 0 0 No loopback. 1 LVDS loopback, transmit to receive on. This control signal is untracked in the ORT4622 core. It is a scratch bit, and its value has no effect on the ORT4622 core. ext ext Switching control master. prot prot sw sw en func 0 -- MUX is controlled by software (one control bit per MUX). Output buffer 3-state signals are controlled by software (one control bit per channel). 1 0 MUX on parallel output bus of channel A is controlled by Prot_Switch A/B pin (0-> channel A, 1-> channel B). MUX on parallel output bus of channel C is controlled by Prot_Switch C/D pin (0 -> channel C, 1-> channel D). Output buffer 3-state signals are controlled by software (one control bit per channel). 1 1 MUX is controlled by software (one control bit per MUX). Output buffer 3-state signals on parallel output bus of channels A and B are controlled by Prot_Switch A/B pin (0-> buffers active, 1-> hi-z). Output buffer 3-state signals on parallel output bus of channels C and D are controlled by Prot_Switch C/D pin (0 -> buffers active, 1-> hi-z).
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Memory Map (continued)
Table 10. Memory Map Bit Descriptions
Bit/Register Name(s) Bit/ Default Register Register Value Location Type (hex) (hex)
Description
Device Register Block (continued)
Rx TOH frame and Rx TOH clock enable serial output port A MUX select 08 [4] creg 0 0 1 09 [0] creg 1 0 1 09 [1] 1 0 1 09 [2] 1 0 1 09 [3] 1 toh_ck_fp_en = 0, can be used to 3-state rx_toh_ck_en and rx_toh_fp signals. Functional Mode. TOH output port A is multiplexed to channel B. TOH output port A is multiplexed to channel A. TOH output port C is multiplexed to channel D. TOH output port C is multiplexed to channel C. Parallel output data bus port A is multiplexed to channel B. Parallel output data bus port A is multiplexed to channel A.
TOH Output MUX Select for Port A
serial output port A MUX select
TOH Output MUX Select for Port C
parallel output port A MUX select
Parallel Port Output MUX Select for Port A
parallel output port A MUX select FIFO aligner threshold value (min) [4:0] FIFO aligner threshold value (max) [4:0]
Parallel Port Output MUX Select for Port C 0 Parallel output data bus port C is multiplexed to channel D. 1 Parallel output data bus port C is multiplexed to channel C. These are the minimum and maximum thresholds values for the per channel receive direction alignment FIFOs. If and when the minimum or maximum threshold value is violated by a particular channel, then the interrupt event FIFO aligner threshold error will be generated for that channel and latched as a FIFO aligner threshold error flag in the respective per STS-12 interrupt alarm register. The allowable range for minimum threshold values is 0 to 23. The allowable range for maximum threshold values is 0 to 22. Note that the minimal and maximum FIFO aligner threshold values apply to all four channels. These three-per-device control signals are used in conjunction with the per-channel A1/A2 error insert command control bits to force A1/A2 errors in the transmit direction. If a particular channel's A1/A2 error insert command control bit is set to the value one, then the A1 and A2 error insert values will be inserted into that channels respective A1 and A2 bytes. The number of consecutive frames to be corrupted is determined by the number of consecutive A1, A2 errors to generate[3:0] control bits. The error insertion is based on a rising edge detector. As such, the control must be set to value 0 before trying to initiate a second A1/A2 corruption. 0 No loopback. 1 Receive to transmit loopback on FPGA side. 0 Even parity. 1 Odd parity.
0A [4:0]
creg
02
0B [4:0]
15
number of consecutive A1/A2 errors to generate [3:0] A1 error insert value [7:0] A2 error insert value [7:0]
0C [3:0]
creg
00
0D [7:0] 0E [7:0]
00 00
line loopback control input/output parallel bus parity control
0C [4] 0C [5]
creg creg
0 0
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Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Memory Map (continued)
Table 10. Memory Map Bit Descriptions
Bit/Register Name(s) Bit/ Register Location (hex) Register Type Default Value (hex) Description
Device Register Block (continued)
scrambler/ descrambler control 0C [6] creg 1 No receive direction descramble/transmit direction scramble. 1 In receive direction, descramble channel after SONET frame recovery. In transmit direction scramble data just before parallel-to-serial conversion. 0 No error insertion. 1 Invert corresponding bit in B1 byte. Consolidation Interrupts 0 No interrupt. Mask interrupt in enable/mask register. 1 Interrupt. Enable interrupt in enable/mask register. 0
transmit B1 error insert mask [7:0] channel A int channel B int channel C int channel D int per device int enable/mask register [4:0] frame offset error flag write to locked register error flag enable/mask register [1:0]
0F [7:0] 10 [0] 10 [1] 10 [2] 10 [3] 10 [4] 11 [4:0] 12 [0] 12 [1]
creg creg creg creg creg creg iereg iareg iareg
00 0 0 0 0 0 0 0 0
13 [1:0]
iereg
0
If in the receive direction the phase offset between any two channels exceeds 17 bytes, then a frame offset error event will be issued. This condition is continuously monitored. If the ORT4622 core memory map has not been unlocked (by writing A1 00 to the lock registers), and any address other than the lockreg registers or scratch pad register is written to, then a write to locked register event will be generated.
Channel Register Block (Channel A, Channel B, Channel C, Channel D)
Rx behavior in LOF 20, 38 50, 68 [0] -- 1 Receive Behavior in LOF 0 1 Force AIS-L control 20, 38, 50, 68 [1] 0 0 1 0 1 0 1 0 1 When receive direction OOF occurs, do not insert AIS-L. When receive direction OOF occurs, insert AIS-L. Do not force AIS-L. Force AIS-L. Do not insert a parity error. Insert parity error in parity bit of receive TOH serial output for as long as this bit is set. Set receive direction K1/K2 bytes to 0. Pass receive direction K1/K2 though pointer mover. Do not insert parity error. Insert parity error in the parity bit of receive direction parallel output bus for as long as this bit is set.
Force AIS-L Control
TOH serial output port par err ins cmd Rx K1/K2 source select parallel output bus parity err ins cmd
20, 38, 50, 68 [2]
--
0
20, 38, 50, 68 [3] 20, 38, 50, 68 [4]
-- --
0 0
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Memory Map (continued)
Table 10. Memory Map Bit Descriptions
Bit/Register Name(s) Bit/ Register Location (hex) Register Type Default Value (hex) Description
Channel Register Block (Channel A, Channel B, Channel C, Channel D) (continued)
channel enable/disable control 20, 38, 50, 68 [5] creg 0 Channel Enable/Disable Control 0 Powerdown channel A/B/C/D CDR and LVDS I/O can be used with data_rx_en to 3-state output buses. 1 Functional mode. To be used as 3-state control for protection switching on the FPGA data output. To be used as 3-state control for TOH data output. Only channel A enable signal is brought out. Transmit Mode of Operation 0 Insert TOH from serial ports. 1 Pass through all TOH. Other Registers 0 Insert TOH from serial ports. 1 Pass through that particular TOH byte. 0 1
Hi-z control of parallel output bus.
20, 38, 50, 68 [6]
creg
0
Hi-z control of TOH data output.
20 [7]
creg
0
Tx mode of operation
21, 39, 51, 69 [7]
creg
0
Tx E1 F2 E2 source select Tx S1 M0 source select Tx K1 K2 source select Tx D12--D9 source select Tx D8--D1 source select A1/A2 error insert command
21, 39, 51, 69 [6] 21, 39, 51, 69 [5] 21, 39, 51, 69 [4] 21, 39, 51, 69 [3:0] 22, 3a, 52, 6a [7:0] 23, 3b, 53, 6b [0]
creg creg creg creg creg creg
B1 error insert command
23, 3b, 53, 6b [1]
creg
concatindication 12, 9, 6, 3 concatindication 11, 8, 5, 2, 10, 7, 4, 1
24, 3c, 54, 6c [3:0] 25, 3d, 55, 6d [7:0]
sreg sreg
per STS-12 alarm flag AIS-P flag elastic store overflow flag enable/mask register [2:0] FIFO aligner threshold error flag receiver internal path parity error flag LOF flag LVDS link B1 parity error flag input parallel bus parity error flag TOH serial input port parity error flag enable/mask register [5:0] AIS interrupt flags 12, 9, 6, 3 AIS interrupt flags 11, 8, 5, 2, 10, 7, 4, 1 enable/mask register 12, 9, 6, 3 enable/mask register 11, 8, 5, 2, 10, 7, 4, 1
26, 3e, 56, 6e [0] 26, 3e, 56, 6e [1] 26, 3e, 56, 6e [2] 27, 3f, 57, 6f [2:0] 28, 40, 58, 70 [0] 28, 40, 58, 70 [1] 28, 40, 58, 70 [2] 28, 40, 58, 70 [3] 28, 40, 58, 70 [4] 28, 40, 58, 70 [5] 29, 41, 59, 71 [5:0] 2a, 42, 5a, 72 [3:0] 2b, 43, 5b, 73 [7:0] 2c, 44, 5c, 74 [3:0] 2d, 45, 5d, 75 [7:0]
isreg isreg isreg iereg iareg iareg iareg iareg iareg iareg iareg iareg iareg iereg iereg
Do not insert error.* Insert error for number of frames in register hex 0C.* 0 0 Do not insert error. 1 Insert error for one frame in B1 bits defined by register hex 0F. 0 The value one in any bit location indi0 cates that STS# is in CONCAT mode. A 0 indicates that the STS is not in CONCAT mode, or is the head of a concat group. 0 These flag register bits per STS-12 0 alarm flag, AIS-P flag, and elastic store 0 overflow flag are the per-channel inter3'b000 rupt status (consolidation) register. 0 These are per the STS-12 alarm flags 0 with the corresponding enable/mask 0 register. 0 0 0 6'h00 4'h0 These are the AIS-P alarm flags with 8'h00 the corresponding enable/mask 4'h0 register. 8'h00
0 0 0 4'h0 8'h00 0
* The error insertion is based on a rising edge detector. As such, the control must be set to value 0 before trying to initiate a second A1/A2 corruption. The error insertion is based on a rising edge detector. As such, the control must be set to value 0 before trying to initiate a second B1 corruption.
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Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Memory Map (continued)
Table 10. Memory Map Bit Descriptions
Bit/Register Name(s) Bit/ Register Location (hex) Register Type Default Value (hex) Description
Channel Register Block (Channel A, Channel B, Channel C, Channel D) (continued)
ES overflow flags 12, 9, 6, 3 ES overflow flags 11, 8, 5, 2, 10, 7, 4, 1 enable/mask register 12, 9, 6, 3 enable/mask register 11, 8, 5, 2, 10, 7, 4, 1 LVDS link B1 parity error counter LOF counter A1/A2 frame error counter 2e, 46, 5e, 76 [7:0] 2f, 47, 5f, 77 [3:0] 30, 48, 60, 78 [7:0] 31, 49, 61, 79 [7:0] 32, 4a, 62, 7a [7:0] 33, 4b, 63, 7b [7:0] 34, 4c, 64, 7c [7:0] -- 4'h0 8'h00 4'h0 8'h00 8'h00 8'h00 8'h00 These are the elastic store overflow alarm flags.
counter counter counter
7-bit count + overflow-reset on read. 7-bit count + overflow-reset on read. 7-bit count + overflow-reset on read.
* The error insertion is based on a rising edge detector. As such, the control must be set to value 0 before trying to initiate a second A1/A2 corruption. The error insertion is based on a rising edge detector. As such, the control must be set to value 0 before trying to initiate a second B1 corruption.
Powerup Sequencing for ORT4622 Device
ORCA Series ORT4622 device uses two power supplies: one to power the device I/Os and the ASIC core (VDD), which is set to 3.3 V for 3.3 V operation and 5 V tolerance on input pins, and another supply for the internal FPGA logic (VDD2), which is set to 2.5 V. It is understood that many users will derive the 2.5 V core logic supply from a 3.3 V power supply, so the following recommendations are made for the powerup sequence of the supplies and allowable delays between power supplies reaching stable voltages. In general, both the 3.3 V and the 2.5 V supplies should ramp-up and become stable as close together in time as possible. There is no delay requirement if the VDD2 (2.5 V) supply becomes stable prior to the VDD (3.3 V) supply. There is a delay requirement imposed if the VDD supply becomes stable prior to the VDD2 supply. The requirement is that the VDD2 (2.5 V) supply transition from 0 V to 2.3 V within 15.7 ms if the VDD (3.3 V) supply is already stable at a minimum of 3.0 V. If the VDD supply has not yet reached 3.0 V when the VDD2 supply has reached 2.3 V, then the requirement is that the VDD2 supply reach a minimum of 2.3 V within 15.7 ms of when the VDD supply reaches 3.0 V. If the chosen power supplies cannot meet this delay requirement, it is always possible to hold off configuration of the FPGA by asserting INIT or PRGM until the VDD2 supply has reached 2.3 V. This process eliminates any power supply sequencing issues.
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
FPGA Configuration Data Format
The ORCA Foundry development system interfaces with front-end design entry tools and provides tools to produce a fully configured FPSC. This section discusses using the ORCA Foundry development system to generate configuration RAM data and then provides the details of the configuration frame format.
FPGA Configuration Data Frame
Configuration data can be presented to the FPSC in two frame formats: autoincrement and explicit. A detailed description of the frame formats is shown in Figure 11, Figure 12, and Table 11. The two modes are similar except that autoincrement mode uses assumed address incrementation to reduce the bit stream size, and explicit mode requires an address for each data frame. In both cases, the header frame begins with a series of 1s and a preamble of 0010, followed by a 24-bit length count field representing the total number of configuration clocks needed to complete the loading of the FPSC. The mandatory ID frame contains data used to determine if the bit stream is being loaded to the correct type of ORCA device (i.e., a bit stream generated for an ORT4622 is being sent to an ORT4622). Error checking is always enabled for Series 3+ devices, through the use of an 8-bit checksum. One bit in the ID frame also selects between the autoincrement and explicit address modes for this load of the configuration data. A configuration data frame follows the ID frame. A data frame starts with a one-start bit pair and ends with enough one-stop bits to reach a byte boundary. If using autoincrement configuration mode, subsequent data frames can follow. If using explicit mode, one or more address frames must follow each data frame, telling the FPSC at what addresses the preceding data frame is to be stored (each data frame can be sent to multiple addresses). Following all data and address frames is the postamble. The format of the postamble is the same as an address frame with the highest possible address value with the checksum set to all ones.
Using ORCA Foundry to Generate Configuration RAM Data
The configuration data bit stream defines the embedded core configuration, the FPGA logic functionality, and the I/O configuration and interconnection. The data bit stream is generated by the ORCA Foundry development tools. The bit stream created by the bit stream generation tool is a series of 1s and 0s used to write the FPSC configuration RAM. It can be loaded into the FPSC using one of the configuration modes discussed elsewhere in this data sheet. For FPSCs, the bit stream is prepared in two separate steps in the design flow. The configuration options of the embedded core are specified using ORCA ORT4622 Design Kit Software at the beginning of the design process. This offers the designer a specific configuration to simulate and design the FPGA logic to. Upon completion of the design, the bit stream generator combines the embedded core options and the FPGA configuration into a single bit stream for download into the FPSC.
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Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
FPGA Configuration Data Format (continued)
CONFIGURATION DATA 0010 01 01 CONFIGURATION DATA 00
PREAMBLE LENGTH COUNT
ID FRAME
CONFIGURATION DATA FRAME 1
CONFIGURATION DATA FRAME 2
POSTAMBLE 5-5759(F)
CONFIGURATION HEADER
Figure 11. Serial Configuration Data Format--Autoincrement Mode
CONFIGURATION DATA 0010 01 00 01
CONFIGURATION DATA 00 00
PREAMBLE LENGTH COUNT
ID FRAME
CONFIGURATION DATA FRAME 1
ADDRESS FRAME 1
CONFIGURATION DATA FRAME 2
ADDRESS FRAME 2
POSTAMBLE 5-5760(F)
CONFIGURATION HEADER
Figure 12. Serial Configuration Data Format--Explicit Mode Table 11. Configuration Frame Format and Contents Header 11110010 24-bit Length Count 11111111 0101 1111 1111 1111 Configuration Mode Reserved [41:0] ID Checksum 11111111 01 Data Bits Alignment Bits = 0 Checksum 11111111 00 14 Address Bits Checksum 11111111 00 11111111 111111 1111111111111111 Preamble. Configuration frame length. Trailing header--8 bits. ID frame header. 00 = autoincrement, 01 = explicit. Reserved bits set to 0. 20-bit part ID. 8-bit checksum. Eight stop bits (high) to separate frames. Data frame header. Number of data bits depends upon device. String of 0 bits added to bit stream to make frame header, plus data bits reach a byte boundary. 8-bit checksum. Eight stop bits (high) to separate frames. Address frame header. 14-bit address of location to start data storage. 8-bit checksum. Eight stop bits (high) to separate frames. Postamble header. Dummy address. 16 stop bits.
ID Frame
Configuration Data Frame (repeated for each data frame) Configuration Address Frame
Postamble
Note: For slave parallel mode, the byte containing the preamble must be 11110010. The number of leading header dummy bits must be (n * 8) + 4, where n is any nonnegative integer and the number of trailing dummy bits must be (n * 8), where n is any positive integer. The number of stop bits/frame for slave parallel mode must be (x * 8), where x is a positive integer. Note also that the bit stream generator tool supplies a bit stream that is compatible with all configuration modes, including slave parallel mode.
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
FPGA Configuration Data Format
(continued)
FPGA Configuration Modes
There are eight methods for configuring the FPSC. Six of the configuration modes are selected on the M0, M1, and M2 input and are shown in Table 12. A fourth input, M3, is used to select the frequency of the internal oscillator, which is the source for CCLK in some configuration modes. The nominal frequencies of the internal oscillator are 1.25 MHz and 10 MHz. The 1.25 MHz frequency is selected when the M3 input is unconnected or driven to a high state. Note that the Master parallel mode of configuration that is available in the ORCA Series 3 FPGAs is not available in the ORT4622. More information on the general FPGA modes of configuration can be found in the ORCA Series 3 data sheet. Table 12. Configuration Modes M2 M1 M0 0 0 0 0 0 1 0 1 0 CCLK Output Input Output Configuration Mode Master Serial Slave Parallel Microprocessor: Motorola* PowerPC Microprocessor: Intel i960 Reserved Async Peripheral Reserved Slave Serial Data Serial Parallel Parallel
Bit Stream Error Checking
There are three different types of bit stream error checking performed in the ORCA Series 3+ FPSCs: ID frame, frame alignment, and CRC checking. The ID data frame is sent to a dedicated location in the FPSC. This ID frame contains a unique code for the device for which it was generated. This device code is compared to the internal code of the FPSC. Any differences are flagged as an ID error. This frame is automatically created by the bit stream generation program in ORCA Foundry. Each data and address frame in the FPSC begins with a frame start pair of bits and ends with eight stop bits set to 1. If any of the previous stop bits were a 0 when a frame start pair is encountered, it is flagged as a frame alignment error. Error checking is also done on the FPSC for each frame by means of a checksum byte. If an error is found on evaluation of the checksum byte, then a checksum/parity error is flagged. When any of the three possible errors occur, the FPSC is forced into an idle state, forcing INIT low. The FPSC will remain in this state until either the RESET or PRGM pins are asserted. If using either of the MPI modes to configure the FPSC, the specific type of bit stream error is written to one of the MPI registers by the FPGA configuration logic. The PGRM bit of the MPI control register can also be used to reset out of the error condition and restart configuration.
0 1 1 1 1
1 0 0 1 1
1 0 1 0 1
Output
Parallel
Output Input
Parallel Serial
* Motorola is a registered trademark of Motorola, Inc. Intel is a registered trademark of Intel Corporation.
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. The ORCA Series 3+ FPSCs include circuitry designed to protect the chips from damaging substrate injection currents and to prevent accumulations of static charge. Nevertheless, conventional precautions should be observed during storage, handling, and use to avoid exposure to excessive electrical stress. Table 13. Absolute Maximum Ratings Parameter Storage Temperature I/O Supply Voltage with Respect to Ground Internal Supply Voltage Input Signal with Respect to Ground CMOS I/O 5 V Tolerant I/O Signal Applied to High-impedance Output Maximum Package Body Temperature Junction Temperature Symbol Tstg VDD VDD2 -- -- -- -- TJ Min -65 -- -- -0.5 -0.5 -0.5 -- -40 Max 150 4.2 3.2 VDD + 0.3 5.8 VDD + 0.3 220 125 V V V C C Unit C V
Recommend Operating Conditions
Table 14. Recommend Operating Conditions ORT4622 Temperature Range (Ambient) 0 C to 70 C I/O Supply Voltage (VDD) 3.3 V 5% Internal Supply Voltage (VDD2) 2.5 V 5%
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Electrical Characteristics
Table 15. General Electrical Characteristics ORT4622 Commercial: VDD = 3.3 V 5%, VDD2 = 2.5 V 5%, 0 C < TA < 70 C. Symbol IDDSB Parameter Standby Current Test Conditions ORT4622 Min -- Max 5.3 Unit mA
IDDSB
VDR IPP
(TA = 25 C, VDD = 3.3 V, VDD2 = 2.5 V) internal oscillator running, no output loads, inputs at VDD or GND (after configuration) Standby Current (TA = 25 C, VDD = 3.3 V, VDD2 = 2.5 V) internal oscillator stopped, no output loads, inputs at VDD or GND (after configuration) Data Retention Voltage TA = 25 C Powerup Current Power supply current at approximately 1 V, within a recommended power supply ramp rate of 1 ms--200 ms
--
1.4
mA
2.3 2.7
-- --
V mA
Table 16. Electrical Characteristics for FPGA I/O ORT4622 Commercial: VDD = 3.3 V 5%, VDD2 = 2.5 V 5%, 0 C < TA < 70 C. Parameter Input Voltage: High Low Input Voltage: High Low Output Voltage: High Low Input Leakage Current Input Capacitance Output Capacitance Symbol Test Conditions Input configured as CMOS (clamped to VDD) Input configured as 5 V tolerant VIH VIL VOH VOL IL CIN COUT VDD = min, IOH = 6 mA or 3 mA VDD = min, IOL = 12 mA or 6 mA VDD = max, VIN = VSS or VDD (TA = 25 C, VDD = 3.3 V, VDD2 = 2.5 V) test frequency = 1 MHz (TA = 25 C, VDD = 3.3 V, VDD2 = 2.5 V) test frequency = 1 MHz -- -- (VDD = 3.6 V, VIN = VSS, TA = 0 C) (VDD = 3.6 V, VIN = VSS, TA = 0 C) VDD = all, VIN = VSS, TA = 0 C VDD = all, VIN = VDD, TA = 0 C 50% VDD GND - 0.5 2.4 -- -10 -- -- 100 100 14.4 26 100 50 5.8 30% VDD -- 0.4 10 8 9 -- -- 50.9 103 -- -- V V V V A pF pF k k A A k k ORT4622 Min 50% VDD GND - 0.5 Max VDD + 0.3 30% VDD Unit
VIH VIL
V V
DONE Pull-up Resistor* RDONE M[3:0] Pull-up Resistors* RM I/O Pad Static Pull-up IPU Current* I/O Pad Static Pull-down IPD Current I/O Pad Pull-up Resistor* RPU I/O Pad Pull-down Resistor RPD
* The pull-up resistor will externally pull the pin to a level 1.0 V below VDD.
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
(continued)
Electrical Characteristics
Table 17. Electrical Characteristics for Embedded Core I/O Other than LVDS I/O Symbol VIH VIL VOH VOH Parameter Input High Voltage (TTL input) Input Low Voltages (TTL input) Output High Voltage (TTL output) Output Low Voltage (TTL output) Min 2.0 -- 2.4 -- Max 5.5 0.8 -- 0.4 Unit V V V V
Note: All outputs are driving 35 pF, except CPU data bus pins which drive 100 pF. It is assumed that the TTL buffers from the standard-cell library can handle the 100 pF load.
HSI Circuit Specifications
Input Data
The 622 Mbits/s scrambled input data stream must conform to SONET STS-12 and SDH STM-4 data format using either a PN7 or PN9 sequence. The PN7 characteristic is 1 + x6 + x7 and the PN9 characteristic is 1 + x4 + x9. The ORT4622 supplies a default scrambler using the PN7 sequence. The longest allowable stream of nontransitional 622 Mbits/s input data is 60 bits. This sequence should not occur more often than once per minute. An input signal phase change of no more than 100 ps is allowed over 200 ns time interval, which translates to a frequency change of 500 ppm. The signal eye opening must be greater than 0.4 UIp-p (unit interval peak-to-peak), and the unit interval for 622 Mbits/s is 1.6075 ns.
PLL
PLL requires an external 10 k pull-down resistor. Table 19. PLL Parameter Loop Bandwidth Jitter Peaking Powerup Reset Duration Lock Acquisition Min -- -- 10 -- Max 6 2 -- 1 Unit MHz dB s ms
Input Reference Clock
Table 20. Input Reference Clock Parameter Frequency Deviation Frequency Change Phase Change in 200 ns Min -- -- -- Max 20 ppm 500 ppm 100 ps
Jitter Tolerance
The input jitter tolerance of the ORT4622 is shown in Table 18. Table 18. Jitter Tolerance Frequency 250 kHz 25 kHz 2 kHz UIp-p 0.6 6.0 60
Generated Output Jitter
The generated output jitter is a maximum of 0.2 UIp-p from 250 kHz to 5 MHz.
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
HSI Circuit Specifications
(continued)
Power Supply Decoupling LC Circuit
The 622 MHz HSI macro contains both analog and digital circuitry. The data recovery function, for example, is implemented as primarily a digital function, but it relies on a conventional analog phase-locked loop to provide its 622 MHz reference frequency. The internal analog phase-locked loop contains a voltage-controlled oscillator. This circuit will be sensitive to digital noise generated from the rapid switching transients associated with internal logic gates and parasitic inductive elements. Generated noise that contains frequency components beyond the bandwidth of the internal phase-locked loop (about 3 MHz) will not be attenuated by the phase-locked loop and will impact bit error rate directly. Thus, separate power supply pins are provided for these critical analog circuit elements. Additional power supply filtering in the form of a LC pi filter section will be used between the power supply source and these device pins as shown in Figure 13. The corner frequency of the LC filter is chosen based on the power supply switching frequency, which is between 100 kHz and 300 kHz in most applications. Capacitors C1 and C2 are large electrolytic capacitors to provide the basic cutoff frequency of the LC filter. For example, the cutoff frequency of the combination of these elements might fall between 5 kHz and 50 kHz. Capacitor C3 is a smaller ceramic capacitor designed to provide a low-impedance path for a wide range of high-frequency signals at the analog power supply pins of the device. The physical location of capacitor C3 must be as close to the device lead as possible. Multiple instances of capacitors C3 can be used if necessary. The recommended filter for the HSI macro is shown below: L = 4.7 H, RL = 1 , C1 = 0.01 F, C2 = 0.01 F, C3 = 4.7 F.
FROM POWER SUPPLY SOURCE
L
TO DEVICE PLL_VDDA
+
C1
+
C2
+
C3 PLL_VSSA
5-9344(F)
Figure 13. Sample Power Supply Filter Network for Analog HSI Power Supply Pins
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
LVDS I/O
Table 21. LVDS Driver dc Data* Parameter Driver Output Voltage High, VOA or VOB Driver Output Voltage Low, VOA or VOB Driver Output Differential Voltage VOD = (VOA - VOB) (with External Reference Resistor) Driver Output Offset Voltage VOS = (VOA + VOB)/2 Output Impedance, Single Ended RO Mismatch Between A and B Change in |VOD| Between 0 and 1 Change in |VOS| Between 0 and 1 Output Current Output Current Power-off Output Leakage Symbol VOH VOL VOD Test Conditions RLOAD = 100 1% RLOAD = 100 1% RLOAD = 100 1% Min -- 0.925* 0.25 Typ -- -- -- Max 1.475* -- 0.45* Unit V V V
VOS Ro delta RO -- -- ISA, ISB ISAB |xa|, |xb|
RLOAD = 100 1% VCM = 1.0 V and 1.4 V VCM = 1.0 V and 1.4 V RLOAD = 100 1% RLOAD = 100 1% Driver shorted to ground Drivers shorted together VDD = 0 V VPAD, VPADN = 0 V--3 V
1.125* 40 -- -- -- -- -- --
-- 50 -- -- -- -- -- --
1.275* 60 10 25 25 24 12 30
V % mV mV mA mA A
* External reference, REF10 = 1.0 V 3%, REF14 = 1.4 V 3%
Table 22. LVDS Driver ac Data Parameter VOD Fall Time, 80% to 20% VOD Rise Time, 20% to 80% Differential Skew |tpHLA - tpLHB| or |tpHLB - tpLHA| Channel-to-channel Skew |tpDIFFm - tpDIFFn|, Propagation Delay Time Symbol TFALL TRISE TSKEW1 Test Conditions ZLOAD = 100 1% CPAD = 3 pF, CPAD = 3 pF ZLOAD = 100 1% CPAD = 3 pF, CPAD = 3 pF Any differential pair on package at 50% point of the transition Any two signals on package at 0 V differential ZLOAD = 100 W 1% CPAD = 3 pF, CPADN = 3 pF Min 100 100 -- Max 200 200 50 Unit ps ps ps
TSKEW2 TPLH TPHL
-- 0.50 0.55
-- 0.90 1.03
ps ps
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Preliminary Data Sheet March 2000
LVDS I/O (continued)
LVDS Receiver Buffer Requirements
Table 23. LVDS Receiver dc Data Parameter Receiver Input Voltage Range, VIA or VIB Receiver Input Differential Threshold Receiver Input Differential Hysteresis Receiver Differential Input Impedance Symbol VI |VIDTH| VHYST RIN Test Conditions |VGPD| < 925 mVdc 1 MHz |VGPD| < 925 mV 400 MHz VIDTHH - VIDTHL With built-in termination, center-tapped Min 0 -100 -- 80 Typ 1.2 -- -- 100 Max 2.4 100 --* 120 Unit V mV mV
* Buffer will not produce output transition when input is open-circuited. Note: VDD = 3.1 V--3.5 V, 0 C --125 C, slow-fast process.
Table 24. LVDS Receiver ac Data Symbol TPWD TPLH, TPHL -- TRISE TFALL Parameter Receiver Output Pulse-width Distortion Propagation Delay Time With Common-mode Variation, (0 V to 2.4 V) Receiver Output Signal Rise Time, VOD 20% to 80% Receiver Output Signal Fall Time, VOD 80% to 20% Test Conditions |VIDTH| = 100 mV 311 MHz CL = 1.5 pF CL = 1.5 pF CL = 1.5 pF CL = 1.5 pF Min -- 0.75 0.74 -- 150 150 Max TBD 1.65 1.82 50 350 350 Unit ps ns ps ps ps
Table 25. LVDS Receiver Power Consumption Symbol PRdc PRac Parameter Receiver dc Power Receiver ac Power Test Conditions dc ac, CL = 1.5 pF Min -- -- Max 34.8 0.026 Unit mW mW/MHz
Table 26. LVDS Operating Parameters Parameter Transmit Termination Resistor Receiver Termination Resistor Temperature Range Power Supply VDD Power Supply VSS Test Conditions -- -- -- -- -- Min -- -- -40 3.1 -- Normal 100 50 -- -- 0 Max -- -- 125 3.5 -- Unit C V V
Note: Under worst-case operating condition, the LVDS driver will withstand a disabled or unpowered receiver for an unlimited period of time without being damaged. Similarly, when outputs are short-circuited to each other or to ground, the LVDS will not suffer permanent damage. The LVDS driver supports hot-insertion. Under a well-controlled environment, the LVDS I/O can drive backplane as well as cable.
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Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Table 27. Derating for Commercial Devices (I/O Supply VDD) TJ (C) -40 0 25 85 100 125 Power Supply Voltage 3.0 V 0.82 0.91 0.98 1.00 1.23 1.34 3.3 V 0.72 0.80 0.85 0.99 1.07 1.15 3.6 V 0.66 0.72 0.77 0.90 0.94 1.01
Timing Characteristics
Description
The most accurate timing characteristics are reported by the timing analyzer in the ORCA Foundry development system. A timing report provided by the development system after layout divides path delays into logic and routing delays. The timing analyzer can also provide logic delays prior to layout. While this allows routing budget estimates, there is wide variance in routing delays associated with different layouts. The logic timing parameters noted in the Electrical Characteristics section of this data sheet are the same as those in the design tools. In the PFU timing, symbol names are generally a concatenation of the PFU operating mode and the parameter type. The setup, hold, and propagation delay parameters, defined below, are designated in the symbol name by the SET, HLD, and DEL characters, respectively. The values given for the parameters are the same as those used during production testing and speed binning of the devices. The junction temperature and supply voltage used to characterize the devices are listed in the delay tables. Actual delays at nominal temperature and voltage for best-case processes can be much better than the values given. It should be noted that the junction temperature used in the tables is generally 85 C. The junction temperature for the FPGA depends on the power dissipated by the device, the package thermal characteristics (JA), and the ambient temperature, as calculated in the following equation and as discussed further in the Package Thermal Characteristics Summary section: TJmax = TAmax + (P * JA) C Note: The user must determine this junction temperature to see if the delays from ORCA Foundry should be derated based on the following derating tables. Table 27 and Table 28 provide approximate power supply and junction temperature derating for OR3LP26B commercial devices. The delay values in this data sheet and reported by ORCA Foundry are shown as 1.00 in the tables. The method for determining the maximum junction temperature is defined in the Package Thermal Characteristics section. Taken cumulatively, the range of parameter values for best-case vs. worst-case processing, supply voltage, and junction temperature can approach three to one.
Table 28. Derating for Commercial Devices (I/O Supply VDD2) TJ (C) -40 0 25 85 100 125 Power Supply Voltage 2.38 V 0.86 0.94 0.99 1.00 1.23 1.33 2.5 V 0.71 0.79 0.84 0.99 1.05 1.13 2.63 V 0.67 0.73 0.77 0.92 0.96 1.03
Note: The derating tables shown above are for a typical critical path that contains 33% logic delay and 66% routing delay. Since the routing delay derates at a higher rate than the logic delay, paths with more than 66% routing delay will derate at a higher rate than shown in the table. The approximate derating values vs. temperature are 0.26% per C for logic delay and 0.45% per C for routing delay. The approximate derating values vs. voltage are 0.13% per mV for both logic and routing delays at 25 C.
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Timing Characteristics (continued)
Propagation Delay--The time between the specified reference points. The delays provided are the worstcase of the tphh and tpll delays for noninverting functions, tplh and tphl for inverting functions, and tphz and tplz for 3-state enable. Setup Time--The interval immediately preceding the transition of a clock or latch enable signal, during which the data must be stable to ensure it is recognized as the intended value. Hold Time--The interval immediately following the transition of a clock or latch enable signal, during which the data must be held stable to ensure it is recognized as the intended value. 3-State Enable--The time from when a 3-state control signal becomes active and the output pad reaches the high-impedance state.
PIO Timing
Refer to ORCA Series 3 data sheet for the following: Programmable I/O (PIO) Timing Characteristics
Special Function Timing
Refer to ORCA Series 3 data sheet for the following: Microprocessor Interface (MPI) Timing Characteristics Programmable Clock Manager (PCM) Timing Characteristics Boundary-Scan Timing Characteristics
Clock Timing
Refer to ORCA Series 3 data sheet for the following:
ExpressCLK (ECLK) and Fast Clock (FCLK) Timing Characteristics
PFU Timing
Refer to ORCA Series 3 data sheet for the following: Combination PFU Timing Characteristics Sequential PFU Timing Characteristics Ripple Mode PFU Timing Characteristics Synchronous Memory Write Characteristics Synchronous Memory Read Characteristics
General-Purpose Clock Timing Characteristics (Internally Generated Clock) ORT4622 ExpressCLK to Output Delay (Pin-to-Pin) ORT4622 Fast Clock (FCLK) to Output Delay (Pin-toPin) ORT4622 General System Clock (SCLK) to Output Delay (Pin-to-Pin) ORT4622 Input to ExpressCLK (ECLK) Fast Capture Setup/Hold Time (Pin-to-Pin) ORT4622 Input to Fast Clock Setup/Hold Time (Pin-toPin) ORT4622 Input to General System Clock Setup/Hold Time (Pin-to-Pin)
PLC Timing
Refer to ORCA Series 3 data sheet for the following: PFU Output MUX and Direct Routing Timing Characteristics
Configuration Timing
Refer to ORCA Series 3 data sheet for Configuration Timing Characteristics.
SLIC Timing
Refer to ORCA Series 3 data sheet for the following: Supplemental Logic and Interconnect Cell (SLIC) Timing Characteristics
Readback Timing
Refer to ORCA Series 3 data sheet for Readback Timing Characteristics.
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Timing Characteristics (continued)
Table 29. ORT4622 Embedded Core and FPGA Interface Clock Operation Frequencies ORT4622 Commercial: VDD = 3.3 V 5%, VDD2 = 2.5 V 5%, 0 C < TA < 70 C. Description (TI = 85 C, VDD = min, VDD2 = min) Signal sys_clk toh_clk
* The sys_clk clock frequency is based on the HSI macro specifications.
Speed -7 Min 0 0 Typ --* 25 Max 77.76* 77.76
Unit MHz MHz
All embedded core/FPGA on-chip interface timing is available in ORCA Foundry through the STAMP timing file included in the ORT4622 Design Kit.
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Timing Characteristics (continued)
Clock Timing
TP TL FPGA_SYSCLK TH SYS_FP
DATA_TX BUS (DATA BUS FROM FPGA TO EMBEDDED CORE)
FIRST A1 OF STS1 #1
5-8605 (F)
Figure 14. Transmit Parallel Port Timing (Backplane -> FPGA) Table 30. Timing Requirements (Transmit Parallel Port Timing) Symbol TP TL TH Parameter Clock Period Clock Low Time Clock High Time Min 12.86 5.1 5.1 Nom -- 6.43 6.43 Max -- 7.7 7.7 Unit ns ns ns
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Timing Characteristics (continued)
TPROP SYS_CLK
SYS_FP
DATA_TX BUS (PARALLEL DATA FROM FPGA TO EMBEDDED CORE) HDOUT (LVDS DATA OUT)
A1 OF STS1 #1
FIRST A1 OF STS1 #1
5-8606
Figure 15. Transmit Transport Delay (FPGA -> Backplane) Table 31. Timing Requirements (Transmit Transport Delay) Symbol TPROP Parameter Number of Clocks of Delay from Parallel Bus Input to LVDS Output Min 4 Nom 7 Max 8 Unit SYS_CLK
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Timing Characteristics (continued)
TP TL SYS_CLK TH LINE_FP
DATA_RX BUS (FROM EMBEDDED CORE TO FPGA) PARITY, SPE, C1J1 PINS
FIRST A1 OF STS1 #1
5-8607 (F)
Figure 16. Receive Parallel Port Timing Table 32. Timing Requirements (Receive Parallel Port Timing) Symbol TP TL TH Parameter Clock Period Clock Low Time Clock High Time Min 12.86 5.1 5.1
(Backplane -> FPGA)
Nom -- 6.43 6.43
Max -- 7.7 7.7
Unit ns ns ns
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Timing Characteristics (continued)
TTR SYS_CLK ...
PROT_SW_A OR PROT_SW_C
DATA_RX BUS* A OR C
CH A/C
CH A/C
CH A/C
CH A/C THIZ
...
CH B/D TCH
SYS_CLK
...
DATA_RX BUS A & B OR C&D
CH A & B/ CH C & D
CH A & B/ CH C & D
CH A & B/ CH C & D
CH A & B/ CH C & D
...
5-8608 (F)
* Data bus refers to 8 bits data, 1 bit parity, 1 bit SPE, and 1 bit C1J1. Channel A or C refers to whether the PROT_SW_A or PROT_SW_C pins that are activated. For example, if the PROT_SW_A pin is activated, the timing diagram for output bus A or C refers to output bus A.
Figure 17. Protection Switch Timing Table 33. Timing Requirements (Protection Switch Timing) Symbol TTR THIZ TCH Parameter Transport Delay from Latching of PROT_SW_A/C to Actual Data Switch Transport Delay from Latching of PROT_SW_A/C to Actual Hi-z Propagation Delay from SYS_CLK to HI-Z of Output Bus Min 7 4 -- Nom 8 5 -- Max 9 6 25 Unit Leading edge SYS_CLKs Leading edge SYS_CLKs Leading edge SYS_CLKs
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Timing Characteristics (continued)
SYS_CLK
...
SYS_FP ROW #1
... ROW #9
DATA_TX BUS (PARALLEL BUS)
36 bytes TOH GUARD BAND (4 TOH CLK)
1044 bytes SPE
... GUARD BAND (4 TOH CLK)
1044 bytes SPE
36 bytes TOH
TP THI TLO ...
TOH_CLK
TX TOH_ CLK_ENA
...
TOH SERIAL INPUT
...
MSbit(7) OF B1 byte STS1 #1
bit 6 OF B1 byte STS1 #1 5-8609 (F)
Figure 18. TOH Input Serial Port Timing (FPGA -> Backplane) Table 34. Timing Requirements (TOH Input Serial Port Timing) Symbol TP THI TLO Parameter Clock Period Clock High Time Clock Low Time Min 12.86 5.1 5.1 Nom -- 6.43 6.43 Max 40 7.7 7.7 Unit ns ns ns
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Timing Characteristics (continued)
ROW #1 HDIN (INPUT LVDS SERIAL 622M DATA)
ROW #9
36 bytes TOH
1044 bytes SPE TTRANS_SYS
...
1044 bytes SPE
36 bytes TOH
TTRANS_TOH
TOH_CLK
...
RX TOH FP
...
RX TOH CLK ENA
...
TOH SERIAL OUTPUT
...
MSbit(7) OF A1 byte STS #1
bit 6 OF A1 byte STS #1
bit 0 OF A1 byte STS #1
5-8610 (F)
Note: The total delay from A1 STS1 #1 arriving at LVDS input to RX_TOH_FP is 56 SYS_CLKs and 6 TOH_CLKs. This will vary by 14 SYS_CLKs, 12 each way for the FIFO alignment, and 2 SYS_CLKs due to the variability in the clock recovery of the HSI macro.
Figure 19. TOH Output Serial Port Timing (Backplane -> FPGA) Table 35. Timing Requirements (TOH Output Serial Port Timing) Symbol Parameter Min 44 -- Nom 56 6 Max 68 -- Unit SYS_CLKs TOH_CLKs
TTRANS_SYS Delay from First A1 LVDS Serial Input to Transfer to TOH_CLK TTRANS_TOH Delay from Transfer to TOH_CLK to RX_TOH_FP
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Timing Characteristics (continued)
TACCESS_MIN TPULSE CPU_CS_N (CS_N) TRD_WR_N, ADDR_MAX, DB_HOLD CPU_RD_WR_N (RD_WR_N) CPU_ADDR[6:0] (ADDR[6:0]) CPU_DATA[7:0] (DB[7:0]) INTERNAL REGISTER (SYS_CLK DOMAIN) TADDR_MAX TDAT_MAX RD_WR_MAX TWRITE_MAX CPU_INT_N (INT_N)
DATA VALID
OLD VALUE
NEW VALUE
TINT_MAX
5-8611 (F)
Note: The CPU interface can be bit stream selected either from device I/O or FPGA interface. The timing diagram applies to both interfaces, but not to the FPGA MPI block.
Figure 20. CPU Write Transaction Table 36. Timing Requirements (CPU Write Transaction) Symbol TPULSE TADDR_MAX TDAT_MAX TRD_WR_MAX TWRITE_MAX TACCESS_MIN Parameter Minimum Pulse Width for CS_N Maximum Time from Negative Edge of CS_N to ADDR Valid Maximum Time from Negative Edge of CS_N to Data Valid Maximum Time from Negative Edge of CS_N to Negative Edge of RD_WR_N Maximum Time from Negative Edge of CS_N to Contents of Internal Register Latching DB[7:0] Minimum Time Between a Write Cycle (falling edge of CS_N) and Any Other Transaction (read or write at falling edge of CS_N) Maximum Time from Register FF to Pad Minimum Hold Time that RD_WR_N, ADDR and DB Must be Held Valid from the Negative Edge of CS_N Min 5 -- -- -- -- 60 Max -- 18 25 26 60 -- Unit ns ns ns ns ns ns
TINT_MAX TRW_WR_N,
ADDR, DB_HOLD
-- 57
20 --
ns ns
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Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Timing Characteristics (continued)
TACCESS_MIN TPULSE CPU_CS_N (CS_N) CPU_RD_WR_N (RD_WR_N) CPU_ADDR[6:0] (ADDR[6:0]) THIZ_MAX CPU_DATA[7:0] (DB[7:0]) DATA VALID
TADDR_MAX TRD_WR_MAX TDATA_MAX
5-8612 (F)
Notes: The CPU interface can be bit stream selected either from device I/O or FPGA interface. The timing diagram applies to both interfaces, but not to the FPGA MPI block. The time delay between the advanced SYS_CLK and the distributed SYS_CLK used to sample CS_N is of no consequence. However, the path delay of CS_N from pad to where is it sampled by SYS_CLK must be minimized. The calculated delays assume a 100 pF loading on the DB pins.
Figure 21. CPU Read Transaction Table 37. Timing Requirements (CPU Read Transaction) Symbol TPULSE TADDR_MAX TRD_WR_MAX TDATA_MAX THIZ_MAX TACCESS_MIN Parameter Minimum Pulse Width for CS_N Maximum Time from Negative Edge of CS_N to ADDR Valid Maximum Time from Negative Edge of CS_N to RD_WR_N Falling Maximum Time from Negative Edge of CS_N to Data Valid on DB Port Maximum Time from Rising Edge of CS_N to DB Port Going HI-Z Minimum Time Between a Read Cycle (falling edge of CS_N) and Any Other Transaction (read or write at falling edge of CS_N) Min 5 -- -- -- -- 60 Max -- 5 5 56 12 -- Unit ns ns ns ns ns ns
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Input/Output Buffer Measurement Conditions (on-LVDS Buffer)
VCC GND
TO THE OUTPUT UNDER TEST 50 pF TO THE OUTPUT UNDER TEST
1 k
50 pF
A. Load Used to Measure Propagation Delay
B. Load Used to Measure Rising/Falling Edges
5-3234(F)
Note: Switch to VDD for TPLZ/TPZL; switch to GND for TPHZ/TPZH.
Figure 22. ac Test Loads
ts[i]
out[i]
PAD ac TEST LOADS (SHOWN ABOVE) OUT
VDD out[i] VDD/2 VSS PAD 1.5 V OUT 0.0 V TPLL TPHH
5-3233.a(F)
Figure 23. Output Buffer Delays
PAD IN
in[i]
3.0 V PAD IN 1.5 V 0.0 V VDD in[i] VDD/2 VSS TPLL TPHH
5-3235(F)
Figure 24. Input Buffer Delays 56 Lucent Technologies Inc. Lucent Technologies Inc.
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
FPGA Output Buffer Characteristics
110 100 90 OUTPUT CURRENT, IO (mA) 80 70 60 IOH 50 40 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT VOLTAGE, VO (V)
5-6865(F)
90 IOL OUTPUT CURRENT, IO (mA) 80 IOL 70 60 50 40 IOH 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT VOLTAGE, VO (V)
5-6866(F)
Figure 25. Sinklim (TJ = 25 C, VDD = 3.3 V)
140 IOL 120 OUTPUT CURRENT, IO (mA) 100 80 60 40 20 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT VOLTAGE, VO (V)
5-6867(F)
Figure 28. Sinklim (TJ = 125 C, VDD = 3.0 V)
120 IOL 100 OUTPUT CURRENT, IO (mA)
80
60 IOH 40
IOH
20 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT VOLTAGE, VO (V)
5-6868(F)
Figure 26. Slewlim (TJ = 25 C, VDD = 3.3 V)
140 IOL 120 OUTPUT CURRENT, IO (mA) 100 80 60 40 20 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT VOLTAGE, VO (V)
5-6867(F)
Figure 29. Slewlim (TJ = 125 C, VDD = 3.0 V)
120 IOL 100 OUTPUT CURRENT, IO (mA)
80
60 IOH 40
IOH
20 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT VOLTAGE, VO (V)
5-6868(F)
Figure 27. Fast (TJ = 25 C, VDD = 3.3 V) Lucent Technologies Inc. Lucent Technologies Inc.
Figure 30. Fast (TJ = 125 C, VDD = 3.0 V) 57
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
LVDS Buffer Characteristics
Termination Resistor
The LVDS drivers and receivers operate on a 100 differential impedance, as shown below. External resistors are not required. The differential driver and receiver buffers include termination resistors inside the device package as shown in Figure 31 below.
LVDS DRIVER LVDS RECEIVER
100
50 CENTER TAP 50
EXTERNAL DEVICE PINS
5-8703(F)
Figure 31. LVDS Driver and Receiver and Associated Internal Components
LVDS Driver Buffer Capabilities
Under worst-case operating condition, the LVDS driver must withstand a disabled or unpowered receiver for an unlimited period of time without being damaged. Similarly, when its outputs are short-circuited to each other or to ground, the LVDS driver will not suffer permanent damage. Figure 32 illustrates the terms associated with LVDS driver and receiver pairs.
DRIVER
INTERCONNECT
RECEIVER
VOA
A
AA
VIA
VOB
B
BB
VIB
VGPD
5-8704(F)
Figure 32. LVDS Driver and Receiver
CA VOA A RLOAD VOB B CB V VOD = (VOA - VOB)
5-8705(F)
Figure 33. LVDS Driver 58 Lucent Technologies Inc. Lucent Technologies Inc.
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Estimating Power Dissipation
The total operating power dissipated is estimated by summing the FPGA standby (IDDSB), internal, and external power dissipated, in addition to the embedded block power. Table 38. Embedded Block Power Dissipation Number of Active Channels 1 channel 2 channels 3 channels 4 channels
Note: Power is calculated assuming an activity factor of 20%.
Operating Frequency (Hz) 622 622 622 622
Estimated Power Dissipated (Watt) Min -- -- -- -- Max 1.08 1.43 1.73 2.01
The following discussion relates to the FPGA portion of the device. The internal and external power is the power consumed in the PLCs and PICs, respectively. In general, the standby power is small and may be neglected. The total operating power is as follows: PT = PPLC + PPIC The internal operating power is made up of two parts: clock generation and PFU output power. The PFU output power can be estimated based upon the number of PFU outputs switching when driving an average fan-out of two: PPFU = 0.078 mW/MHz For each PFU output that switches, 0.136 mW/MHz needs to be multiplied times the frequency (in MHz) that the output switches. Generally, this can be estimated by using one-half the clock rate, multiplied by some activity factor; for example, 20%. The power dissipated by the clock generation circuitry is based upon four parts: the fixed clock power, the power/ clock branch row or column, the clock power dissipated in each PFU that uses this particular clock, and the power from the subset of those PFUs that are configured as synchronous memory. Therefore, the clock power can be calculated for the four parts using the following equations:
ORT4622 Clock Power
P = [0.22 mW/MHz + (0.39 mW/MHz/Branch) (# Branches) + (0.008 mW/MHz/PFU) (# PFUs) + (0.002 mW/MHz/PIO (# PIOs)] For a quick estimate, the worst-case (typical circuit) ORT4622 clock power = 4.8 mW/MHz The power dissipated in a PIC is the sum of the power dissipated in the four PIOs in the PIC. This consists of power dissipated by inputs and ac power dissipated by outputs. The power dissipated in each PIO depends on whether it is configured as an input, output, or input/output. If a PIO is operating as an output, then there is a power dissipation component for PIN, as well as POUT. This is because the output feeds back to the input. The power dissipated by an input buffer is (VIH = VDD - 0.3 V or higher) estimated as: PIN = 0.09 mW/MHz The ac power dissipation from an output or bidirectional is estimated by the following: POUT = (CL + 8.8 pF) x VDD2 x F Watts where the unit for CL is farads, and the unit for F is Hz. Lucent Technologies Inc. Lucent Technologies Inc. 59
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Pin Information
This section describes the pins and signals that perform FPGA-related functions. During configuration, the userprogrammable I/Os are 3-stated and pulled-up with an internal resistor. If any FPGA function pin is not used (or not bonded to package pin), it is also 3-stated and pulled-up after configuration. Table 39. FPGA Common-Function Pin Description Symbol Dedicated Pins VDD VDD2 GND RESET -- -- -- I 3.3 V power supply. 2.5 V power supply Ground supply. During configuration, RESET forces the restart of configuration and a pull-up is enabled. After configuration, RESET can be used as an FPGA logic direct input, which causes all PLC latches/FFs to be asynchronously set/reset. I/O Description
CCLK
I/O In the master and asynchronous peripheral modes, CCLK is an output, which strobes configuration data in. In the slave or synchronous peripheral mode, CCLK is input synchronous with the data on DIN or D[7:0]. In microprocessor mode, CCLK is used internally and output for daisy-chain operation. I O As an input, a low level on DONE delays FPGA start-up after configuration.* As an active-high, open-drain output, a high level on this signal indicates that configuration is complete. DONE has a permanent pull-up resistor. PRGM is an active-low input that forces the restart of configuration and resets the boundary-scan circuitry. This pin always has an active pull-up. This pin must be held high during device initialization until the INIT pin goes high. This pin always has an active pull-up. During configuration, RD_CFG is an active-low input that activates the TS_ALL function and 3-states all of the I/O. After configuration, RD_CFG can be selected (via a bit stream option) to activate the TS_ALL function as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on RD_CFG will initiate readback of the configuration data, including PFU output states, starting with frame address 0. RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides configuration data out. If used in boundary scan, TDO is test data out.
DONE
PRGM RD_CFG
I I
RD_DATA/TDO
O
Special-Purpose Pins M0, M1, M2 I During powerup and initialization, M0, M1, and M2 are used to select the configuration mode with their values latched on the rising edge off INIT. During configuration, a pull-up is enabled. After configuration, these pins cannot be user-programmable I/Os. During powerup and initialization, M3 is used to select the speed of the internal oscillator during configuration with their values latched on the rising edge of INIT. When M3 is low, the oscillator frequency is 10 MHz. When M3 is high, the oscillator is 1.25 MHz. During configuration, a pull-up is enabled.
M3
I
I/O After configuration, this pin is a user-programmable I/O pin.*
* The ORCA Series 3 FPGA data sheet contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options.
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Pin Information (continued)
Table 39. FPGA Common-Function Pin Description (continued) Symbol TDI, TCK, TMS I/O I Description If boundary scan is used, these pins are test data in, test clock, and test mode select inputs. If boundary scan is not selected, all boundary-scan functions are inhibited once configuration is complete. Even if boundary scan is not used, either TCK or TMS must be held at logic one during configuration. Each pin has a pull-up enabled during configuration. During configuration in peripheral mode, RDY/RCLK indicates another byte can be written to the FPGA. If a read operation is done when the device is selected, the same status is also available on D7 in asynchronous peripheral mode. During the master parallel configuration mode, RCLK is a read output signal to an external memory. This output is not normally used. In i960 microprocessor mode, this pin acts as the address latch enable (ALE) input. High during configuration (HDC) is output high until configuration is complete. It is used as a control output indicating that configuration is not complete. Low during configuration (LDC) is output low until configuration is complete. It is used as a control output indicating that configuration is not complete.
Special-Purpose Pins (continued)
I/O After configuration, these pins are user-programmable I/O.* RDY/RCLK/ MPI_ALE O
O I HDC LDC INIT O O
I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.*
I/O INIT is a bidirectional signal before and during configuration. During configuration, a pull-up is enabled, but an external pull-up resistor is recommended. As an active-low open-drain output, INIT is held low during power stabilization and internal clearing of memory. As an active-low input, INIT holds the FPGA in the wait-state before the start of configuration. I CS0 and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor configuration modes. The FPGA is selected when CS0 is low and CS1 is high. During configuration, a pull-up is enabled. RD is used in the asynchronous peripheral configuration mode. A low on RD changes D7 into a status output. As a status indication, a high indicates ready, and a low indicates busy. WR and RD should not be used simultaneously. If they are, the write strobe overrides. This pin is also used as the microprocessor interface (MPI) data transfer strobe. For PowerPC, it is the transfer start (TS). For i960, it is the address/data strobe (ADS). WR is used in the asynchronous peripheral configuration mode. When the FPGA is selected, a low on the write strobe, WR, loads the data on D[7:0] inputs into an internal data buffer. WR and RD should not be used simultaneously. If they are, the write strobe overrides.
CS0, CS1
I/O After configuration, these pins are user-programmable I/O pins.* RD/MPI_STRB I
I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.* WR I
I/O After configuration, this pin is a user-programmable I/O pin.*
* The ORCA Series 3 FPGA data sheet contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options.
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Preliminary Data Sheet March 2000
Pin Information (continued)
Table 39. FPGA Common-Function Pin Description (continued) Symbol MPI_IRQ MPI_BI MPI_ACK I/O O O O Description MPI active-low interrupt request output.
Special-Purpose Pins (continued)
PowerPC mode MPI burst inhibit output.
In PowerPC mode MPI operation, this is the active-high transfer acknowledge (TA) output. For i960 MPI operation, it is the active-low ready/record (RDYRCV) output. If the MPI is not in use, this is a user-programmable I/O. In PowerPC mode MPI operation, this is the active-low write/active-high read control signals. For i960 operation, it is the active-high write/active-low read control signal. This is the clock used for the synchronous MPI interface. For PowerPC, it is the CLKOUT signal. For i960, it is the system clock that is chosen for the i960 external bus interface.
I/O If the MPI is not in use, this is a user-programmable I/O.
MPI_RW
I
I/O If the MPI is not in use, this is a user-programmable I/O. MPI_CLK I
A[4:0]
I/O If the MPI is not in use, this is a user-programmable I/O. I For PowerPC operation, these are the PowerPC address inputs. The address bit mapping (in PowerPC/FPGA notation) is A[31]/A[0], A[30]/A[1], A[29]/A[2], A[28]/ A[3], A[27]/A[4]. Note that A[27]/A[4] is the MSB of the address. The A[4:2] inputs are not used in i960 MPI mode. I/O If the MPI is not in use, this is a user-programmable I/O. I I For i960 operation, MPI_BE[1:0] provide the i960 byte enable signals, BE[1:0], that are used as address bits A[1:0] in i960 byte-wide operation. During peripheral and slave parallel configuration modes, D[7:0] receive configuration data, and each pin has a pull-up enabled. During serial configuration modes, D0 is the DIN input. D[7:0] are also the data pins for PowerPC microprocessor mode and the address/data pins for i960 microprocessor mode. During slave serial or master serial configuration modes, DIN accepts serial configuration data synchronous with CCLK. During parallel configuration modes, DIN is the D0 input. During configuration, a pull-up is enabled. During configuration, DOUT is the serial data output that can drive the DIN of daisychained slave LCA devices. Data out on DOUT changes on the falling edge of CCLK.
A[1:0]/MPI_BE[1:0] D[7:0]
I/O After configuration, the pins are user-programmable I/O pins.* DIN I
I/O After configuration, this pin is a user-programmable I/O pin.* DOUT O
I/O After configuration, DOUT is a user-programmable I/O pin.*
* The ORCA Series 3 FPGA data sheet contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options.
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Pin Information (continued)
This section describes device I/O signals to/from the embedded core excluding the signals at the CIC boundary. Table 40. FPSC Function Pin Description Symbol HSI LVDS Pins sts_ina sts_inan sts_inb sts_inbn sts_inc sts_incn sts_ind sts_indn sts_outa sts_outan sts_outb sts_outbn sts_outc sts_outcn sts_outd sts_outdn ctap_refa ctap_refb ctap_refc ctap_refd ref10 ref14 reshi reslo rext pll_VDDA pll_VSSA HSI Test Signals tstmode bypass tstclk mreset resetrn resettn I I I I I I Enables CDR test mode. Internal pull-down. Enables bypassing of the 622 MHz clock synthesis with TSTCLK. Internal pull-down. Test clock for emulation of 622 MHz clock during PLL bypass. Internal pulldown. Test mode reset. Internal pull-down. Resets receiver clock division counter. Internal pull-up. Resets transmitter clock division counter. Internal pull-up. I I I I I I I I O O O O O O O O -- -- -- -- I I -- -- -- -- -- LVDS input receiver A. LVDS input receiver A. LVDS input receiver B. LVDS input receiver B. LVDS input receiver C. LVDS input receiver C. LVDS input receiver D. LVDS input receiver D. LVDS output receiver A. LVDS output receiver A. LVDS output receiver B. LVDS output receiver B. LVDS output receiver C. LVDS output receiver C. LVDS output receiver D. LVDS output receiver D. LVDS input center tap (RX A) (use 0.01 F to GND). LVDS input center tap (RX B) (use 0.01 F to GND). LVDS input center tap (RX C) (use 0.01 F to GND). LVDS input center tap (RX D) (use 0.01 F to GND). LVDS reference voltage: 1.0 V 3%. LVDS reference voltage: 1.4 V 3%. Resistor input (use 100 1% to RESLO input). Resistor input. Reference resistor for PLL (10 k to ground). PLL analog VDD (3.3 V 5%). PLL analog VSS (GND). I/O Description
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Preliminary Data Sheet March 2000
Pin Information (continued)
Table 40. FPSC Function Pin Description (continued) Symbol I/O Description
HSI Test Signals (continued) tstshftld ecsel exdnup etoggle loopbken tstphase tstmux[8:0]s CPU Interface Pins db<7:0> addr<6:0> rd_wr_n cs_n int_n MISC System Signals rst_n I Reset the Core only. The FPGA logic is not reset by rst_n. Internal pull-down allows chip to stay in reset state when external driver loses power. System clock (77.76 MHz), 50% duty cycle, also the reference clock of PLL. Internal pull-up. Temperature sensing diode (anode +). Temperature sensing diode (cathode -). Scan test mode input. Internal pull-up. Scan mode enable input. Internal pull-up. LVDS enable used during BSCAN. During normal operation, lvds_en needs to be pulled high. lvds_en needs to be pulled low for boundary scan. sys_dobist is asserted high to start the BIST, and should be kept high during the entire BIST operation. Internal pull-down. This 32-bit serial out RSB signature consists of the 4-bit FSM state and the BIST flag flip-flop states from each SBRIC_RS element. This flag is asserted to one when BIST is complete, and is used for polling the end of BIST. I/O I I I O CPU interface data bus. Internal pull-up. CPU interface address bus. Internal pull-up. CPU interface read/write. Internal pull-up. Chip select. Internal pull-up. Interrupt output. Internal pull-up. Open drain. I I I I I I O Enables the test mode control register for shifting in selected tests by a serial port. Internal pull-down Enables external test control of 622 MHz clock phase selection. Internal pull-down Direction of phase change. Internal pull-down Moves 622.08 MHz clock selection on phase per positive pulse. Internal pull-down Enables 622 Mbits/s loopback mode. Internal pull-down Controls bypass of 16 PLL-generated phases with 16 low-speed phases. Internal pull-down Test mode output port.
sys_clk dxp dxn SCAN and BSCAN Pins* scan_tstmd scanen lvds_en
I -- -- I I I
Universal BIST Controller Pins sys_dobist sys_rssigo bc I O O
* BSCAN pins-TDI, TDO, TCK, and TMS are on FPGA side.
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Pin Information (continued)
In Table 41, an input refers to a signal flowing into the FGPA logic (out of the embedded core) and an output refers to a signal flowing out of the FPGA logic (into the embedded core). Table 41. Embedded Core/FPGA Interface Signal Description Pin Name data_txa<7:0> data_txa_par data_txb<7:0> data_txb_par data_txc<7:0> data_txc_par data_txd<7:0> data_txd_par data_rxa<7:0> data_rxa_par data_rxa_spe data_rxa_c1j1 data_rxa_en data_rxb<7:0> data_rxb_par data_rxb_spe data_rxb_c1j1 data_rxb_en data_rxc<7:0> data_rxc_par data_rxc_spe data_rxc_c1j1 data_rxc_en data_rxd<7:0> data_rxd_par data_rxd_spe data_rxd_c1j1 data_rxd_en toh_clk toh_txa toh_txb toh_txc toh_txd tx_toh_ck_en toh_rxa toh_rxb toh_rxc Lucent Technologies Inc. Lucent Technologies Inc. I/O O O O O O O O O I I I I I I I I I I I I I I I I I I I I O O O O O O I I I Parity for transmitter A. Parallel bus of transmitter B. MSB is bit 7. Parity for transmitter B. Parallel bus of transmitter C. MSB is bit 7. Parity for transmitter C. Parallel bus of transmitter D. MSB is bit 7. Parity for transmitter D. Parallel bus of receiver A. MSB is bit 7. Parity for parallel bus of receiver A. SPE signal for parallel bus of receiver A. C1J1 signal for parallel bus of receiver A. Enable for parallel bus of receiver A. Parallel bus of receiver B. MSB is bit 7. Parity for parallel bus of receiver B. SPE signal for parallel bus of receiver B. C1J1 signal for parallel bus of receiver B. Enable for parallel bus of receiver B. Parallel bus of receiver C. MSB is bit 7. Parity for parallel bus of receiver C. SPE signal for parallel bus of receiver C. C1J1 signal for parallel bus of receiver C. Enable for parallel bus of receiver C. Parallel bus of receiver D. MSB is bit 7. Parity for parallel bus of receiver D. SPE signal for parallel bus of receiver D. C1J1 signal for parallel bus of receiver D. Enable for parallel bus of receiver D. TX and RX TOH serial links clock (25 MHz to 77.76 MHz). TOH serial link for transmitter A. TOH serial link for transmitter B. TOH serial link for transmitter C. TOH serial link for transmitter D. TX TOH serial link clock enable. TOH serial link for receiver A. TOH serial link for receiver B. TOH serial link for receiver C. 65 Description Parallel bus of transmitter A. MSB is bit 7.
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Pin Information (continued)
Table 41. Embedded Core/FPGA Interface Signal Description (continued) Pin Name toh_rxd rx_toh_ck_en rx_toh_fp toh_ck_fp_en toh_en_a cpu_data_tx<7:0> cpu_data_rx<7:0> cpu_addr<6:0> cpu_rd_wr_n cpu_cs_n cpu_int_n sys_fp line_fp fpga_sysclk prot_sw_a prot_sw_c core_ready I/O I I I I I O I O O O I O O I O O I Description TOH serial link for receiver D. RX TOH serial link clock enable. RX TOH serial link frame pulse. A soft register bit available to enable RX TOH clock and frame pulse. RX TOH enable, soft register. "AND" output of resistor channel A enable and hi-z control of TOH data output A. CPU interface data bus. CPU interface data bus. CPU interface address bus. CPU interface read/write. Chip select. Interrupt. System frame pulse for transmitter section. Line frame pulse for receiver section. System clock (77.76 MHz). Protection switching control signal. Protection switching control signal. During powerup and FPGA configuration sequence, the core_ready is held low. At the end of FPGA configuration, the core_ready will be held low for six clock (sys_clk) cycles and then go active-high. Flag indicates that the embedded core is out of its reset state. The alignment FIFO synchronizes and locates the data frames and outputs an optimal frame pulse for the four arriving data streams. 77.76 MHz recovered clock for channel A. 77.76 MHz recovered clock for channel B. 77.76 MHz recovered clock for channel C. 77.76 MHz recovered clock for channel D. Bit stream selection for microprocessor interface selection. A 0 indicates the microprocessor interface on the core side is selected. A 1 selects the CPU interface from the FPGA side.
fifosync_fp
I
cdr_clk_a cdr_clk_b cdr_clk_c cdr_clk_d rb_mp_sel
I I I I I
66
Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Pin Information (continued)
Table 42. Embedded Core/FPGA Interface Signal Locations
Embedded Core/FPGA Interface Site ASB1A ASB1B ASB1C ASB1D CKTOASB1 ASB2A ASB2B ASB2C ASB2D ASB3A ASB3B ASB3C ASB3D ASB4A ASB4B ASB4C ASB4D ASB5A ASB5B ASB5C ASB5D ASB6A ASB6B ASB6C ASB6D ASB7A ASB7B ASB7C ASB7D ASB8A ASB8B ASB8C ASB8D ASB9A ASB9B ASB9C ASB9D ASB10A ASB10B FPGA Input Signal FPGA Output Signal Embedded Core/FPGA Interface Site ASB10C ASB10D ASB11A ASB11B ASB11C ASB11D ASB12A ASB12B ASB12C ASB12D ASB13A ASB13B ASB13C ASB13D ASB14A ASB14B ASB14C ASB14D ASB15A ASB15B ASB15C ASB15D ASB16A ASB16B ASB16C ASB16D ASB17A ASB17B ASB17C ASB17D ASB18A ASB18B ASB18C ASB18D ASB19A ASB19B ASB19C ASB19D ASB20A FPGA Input Signal FPGA Output Signal
toh_rxa toh_rxb toh_rxc toh_rxd -- rx_toh_ck_en rx_toh_fp toh_ck_fp_en toh_en_a data_rxa7 data_rxa6 data_rxa5 data_rxa4 data_rxa3 data_rxa2 data_rxa1 data_rxa0 data_rxa_par data_rxa_spe data_rxa_c1j1 data_rxa_en data_rxtb7 data_rxb6 data_rxb5 data_rxb4 data_rxb3 data_rxb2 data_rxb1 data_rxb0 data_rxb_par data_rxb_spe data_rxb_c1j1 data_rxb_en data_rxc7 data_rxc6 data_rxc5 data_rxc4 data_rxc3 data_rxc2
toh_txa toh_txb toh_txc toh_txd toh_clk -- -- tx_toh_ck_en -- -- -- -- -- -- -- -- -- prot_sw_a -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
data_rxc1 data_rxc0 data_rxc_par data_rxc_spe data_rxc_c1j1 data_rxc_en data_rxd7 data_rxd6 data_rxd5 data_rxd4 data_rxd3 data_rxd2 data_rxd1 data_rxd0 data_rxd_par data_rxd_spe data_rxd_c1j1 data_rxd_en fifosync_fp -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- prot_sw_c -- -- -- -- -- -- -- -- -- -- line_fp sys_fp -- -- data_txa7 data_txa6 data_txa5 data_txa4 data_txa3 data_txa2 data_txa1 data_txa0 data_txb7 data_txb6 data_txb5 data_txb4 data_txb3 data_txb2 data_txb1 data_txb0 data_txa_par data_txb_par data_txc_par data_txd_par data_txc7
Lucent Technologies Inc. Lucent Technologies Inc.
67
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Pin Information (continued)
Table 42. Embedded Core/FPGA Interface Signal Locations (continued)
Embedded Core/FPGA Interface Site ASB20B ASB20C ASB20D ASB21A ASB21B ASB21C ASB21D ASB22A ASB22B ASB22C ASB22D ASB23A ASB23B ASB23C ASB23D ASB24A ASB24B ASB24C FPGA Input Signal FPGA Output Signal Embedded Core/FPGA Interface Site ASB24D ASB25A ASB25B ASB25C ASB25D ASB26A ASB26B ASB26C ASB26D ASB27A ASB27B ASB27C ASB27D ASB28A ASB28B ASB28C ASB28D BMLKCNTL FPGA Input Signal FPGA Output Signal
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- cpu_data_rx7 cpu_data_rx6 cpu_data_rx5
data_txc6 data_txc5 data_txc4 data_txc3 data_txc2 data_txc1 data_txc0 data_txd7 data_txd6 data_txd5 data_txd4 data_txd3 data_txd2 data_txd1 data_txd0 cpu_data_tx7 cpu_data_tx6 cpu_data_tx5
cpu_data_rx4 cpu_data_rx3 cpu_data_rx2 cpu_data_rx1 cpu_data_rx0 cpu_int_n -- -- core_ready -- -- -- -- cdr_clk_a cdr_clk_b cdr_clk_c cdr_clk_d fpga_sysclk
cpu_data_tx4 cpu_data_tx3 cpu_data_tx2 cpu_data_tx1 cpu_data_tx0 cpu_addr6 cpu_addr5 cpu_addr4 cpu_addr3 cpu_addr2 cpu_addr1 cpu_addr0 cpu_rd_wr_n cpu_cs_n -- -- -- --
68
Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Pin Information (continued)
The ORT4622 is pin compatible with a Series 3 OR3L125B device in the same package in terms of VDD, VSS, configuration, and special function pins. The uses and characteristics of the FPGA user I/O pins in the embedded core area of the device have changed to support the ORT4622 functionality. Additionally, the lower-left programmable clock manager (PCM) clock input pin (SECKLL) has been relocated. A "--" indicates the pin is not used and must be left unconnected (cannot be tied to VDD or VSS). Table 43. 432-Pin EBGA Pinout Pin E4 D3 D2 D1 F4 E3 E2 E1 F3 F2 F1 H4 G3 G2 G1 J4 H3 H2 J3 K4 J2 J1 K3 K2 K1 L3 M4 L2 L1 M3 N4 M2 N3 N2 P4 N1 P3 P2 ORT4622 Pad PRD_CFGN PR1D PR1C PR1B PR1A PR2D PR2C PR2B PR2A PR3D PR3C PR3B PR3A PR4D PR4C PR4B VDD2 PR5A PR6C PR6A PR7A PR8D PR8C PR8B PR8A PR9D PR9C PR9B PR9A PR10D PR10A PR11D PR11A PR12D PR12C PR12A PR13D PR13C Function RD_CFG I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O-WR I/O I/O I/O VDD2 I/O I/O I/O I/O-RD/MPI_STRB I/O I/O I/O I/O I/O I/O I/O I/O-CS0 I/O I/O I/O I/O-CS1 I/O I/O I/O I/O I/O Pin P1 R3 R2 R1 T2 T4 T3 U1 U2 U3 V1 V2 V3 W1 V4 W2 W3 Y2 W4 Y3 AA1 AA2 Y4 AA3 AB1 AB2 AB3 AC1 AC2 AB4 AC3 AD2 AD3 AC4 AE1 AE2 AE3 AD4 ORT4622 Pad VDD2 PR14D PR14C PR14B PECKR PR15D PR15C PR15B PR15A PR16D PR16B PR16A PR17D PR17A PR18D PR18B PR18A -- PR19A -- -- -- -- VDD2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Function VDD2 I/O I/O I/O I/O-ECKR I/O I/O I/O I/O I/O I/O I/O I/O I/O-M3 I/O I/O I/O -- M2 -- -- -- -- VDD2 -- -- -- M1 -- -- -- -- -- -- db3 (core) db2 (core) db1 (core) db0 (core) 69
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Pin Information (continued)
Table 43. 432-Pin EBGA Pinout (continued) Pin AF1 AF2 AF3 AG1 AG2 AG3 AF4 AH1 AH2 AH3 AG4 AH5 AJ4 AK4 AL4 AH6 AJ5 AK5 AL5 AJ6 AK6 AL6 AH8 AJ7 AK7 AL7 AH9 AJ8 AK8 AJ9 AH10 AK9 AL9 AJ10 AK10 AL10 AJ11 AH12 AK11 ORT4622 Pad -- -- -- -- VDD2 -- -- -- -- PPRGMN PRESETN PDONE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDD2 -- -- -- -- -- -- -- -- -- -- -- Function db7 (core) db6 (core) db5 (core) db4 (core) VDD2 int_n (core) -- rst_n (core) M0 PRGM RESET DONE rd_wr_n (core) cs_n (core) addr0 (core) addr1 (core) addr2 (core) addr3 (core) addr4 (core) addr5 (core) addr6 (core) tstmux0s (core) tstmux1s (core) tstmux2s (core) tstmux4s (core) tstmux7s (core) tstmux3s (core) VDD2 tstmux6s (core) tstmux5s (core) tstmux8s (core) INIT tstphase (core) loopbken (core) exdnup (core) ecsel (core) etoggle (core) resettn (core) mreset (core) Pin AL11 AJ12 AH13 AK12 AJ13 AK13 AH14 AL13 AJ14 AK14 AL14 AJ15 AK15 AL15 AK16 AH16 AJ16 AL17 AK17 AJ17 AL18 AK18 AJ18 AL19 AH18 AK19 AJ19 AK20 AH19 AJ20 AL21 AK21 AH20 AJ21 AL22 AK22 AJ22 AL23 AK23 ORT4622 Pad -- -- -- -- -- -- -- -- -- -- -- VDD2 -- -- -- PECKB -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDD2 -- -- -- -- -- -- -- -- Function LDC tstshftld (core) resetrn (core) tstclk (core) bypass (core) tstmode (core) HDC -- -- sys_clk (core) -- VDD2 sts_outd (core) sts_outdn (core) -- sts_outc (core) sts_outcn (core) reslo (core) reshi (core) -- ref14 (core) ref10 (core) rext (core) pll_VSSA (core) pll_VDDA (core) sts_outb (core) sts_outbn (core) -- sts_outa (core) sts_outan (core) VDD2 ctap_refd (core) sts_ind (core) sts_indn (core) sts_inc (core) sts_incn (core) ctap_refc (core) sts_inb (core) sts_inbn (core)
70
Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Pin Information (continued)
Table 43. 432-Pin EBGA Pinout (continued) Pin AH22 AJ23 AK24 AJ24 AH23 AL25 AK25 AJ25 AH24 AL26 AK26 AJ26 AL27 AK27 AJ27 AH26 AL28 AK28 AJ28 AH27 AG28 AH29 AH30 AH31 AF28 AG29 AG30 AG31 AF29 AF30 AF31 AD28 AE29 AE30 AE31 AC28 AD29 AD30 AC29 AB28 ORT4622 Pad -- -- -- -- -- -- -- -- -- -- -- -- VDD2 -- -- -- -- -- -- -- PCCLK -- -- -- -- -- -- -- -- -- -- -- VDD2 -- -- -- -- -- -- -- Function ctap_refb (core) sts_ina (core) sts_inan (core) ctap_refa (core) -- -- -- lvds_en (core) scan_tstmd (core) scanen (core) dxp (core) dxn (core) vdd2 sys_dobist (core) sys_rssigo (core) bc (core) -- -- -- -- CCLK -- -- -- -- -- -- -- -- -- -- -- VDD2 -- -- -- -- -- -- -- Pin AC30 AC31 AB29 AB30 AB31 AA29 Y28 AA30 AA31 Y29 W28 Y30 W29 W30 V28 W31 V29 V30 V31 U29 U30 U31 T30 T28 T29 R31 R30 R29 P31 P30 P29 N31 P28 N30 N29 M30 N28 M29 L31 L30 ORT4622 Pad -- -- -- -- -- -- -- -- -- -- -- PL18A PL18C PL18D PL17A PL17C PL17D PL16A PL16C PL16D PL15A PL15B VDD2 PL15D PL14A PL14B PL14C PECKL PL13A PL13D PL12A PL12C PL12D PL11A PL11C PL11D PL10A PL10C VDD2 PL9A Function -- -- -- -- -- -- -- -- -- MPI_IRQ -- I/O-SECKLL I/O I/O I/O-MPI_BI I/O I/O I/O I/O I/O I/O-MPI_RW I/O VDD2 I/O I/O-MPI_CLK I/O I/O I/O-ECKL I/O I/O I/O I/O I/O I/O-A4 I/O I/O I/O I/O VDD2 I/O-A3
Lucent Technologies Inc. Lucent Technologies Inc.
71
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Pin Information (continued)
Table 43. 432-Pin EBGA Pinout (continued) Pin M28 L29 K31 K30 K29 J31 J30 K28 J29 H30 H29 J28 G31 G30 G29 H28 F31 F30 F29 E31 E30 E29 F28 D31 D30 D29 E28 D27 C28 B28 A28 D26 C27 B27 A27 C26 B26 A26 D24 ORT4622 Pad PL9B PL9C PL9D PL8A PL8B PL8C PL8D PL7D PL6B PL6C PL6D PL5D PL4B PL4C VDD2 PL3A PL3B PL3C PL3D PL2A PL2B PL2C PL2D PL1A PL1B PL1C PL1D PRD_DATA PT1A PT1B PT1C PT1D PT2A PT2B PT2C PT2D PT3A PT3B PT3C Function I/O I/O I/O I/O-A2 I/O I/O I/O I/O-A1/MPI_BE1 I/O I/O I/O I/O I/O I/O VDD2 I/O I/O I/O I/O I/O I/O I/O I/O-A0/MPI_BE0 I/O I/O I/O I/O RD_DATA/TDO I/O-TCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin C25 B25 A25 D23 C24 B24 C23 D22 B23 A23 C22 B22 A22 C21 D20 B21 A21 C20 D19 B20 C19 B19 D18 A19 C18 B18 A18 C17 B17 A17 B16 D16 C16 A15 B15 C15 A14 B14 C14 ORT4622 Pad PT3D PT4A PT4B PT4C PT4D VDD2 PT5B PT5C PT5D PT6A PT6D PT7A PT7D PT8A PT8D PT9A PT9D PT10A PT10D PT11A PT11C PT11D PT12A PT12C PT12D PT13A PT13C PT13D PT14A VDD2 PT14C PT14D PT15A PT15B PT15C PECKT PT16A PT16B PT16D Function I/O I/O-TMS I/O I/O I/O VDD2 I/O I/O I/O I/O-TDI I/O I/O I/O I/O I/O I/O I/O I/O-DOUT I/O I/O I/O I/O I/O-D0/DIN I/O I/O I/O I/O I/O-D1 I/O-D2 VDD2 I/O I/O I/O-D3 I/O I/O I/O-ECKT I/O-D4 I/O I/O
72
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Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Pin Information (continued)
Table 43. 432-Pin EBGA Pinout (continued) Pin A13 D14 B13 C13 B12 D13 C12 A11 B11 D12 C11 A10 B10 C10 A9 B9 D10 C9 B8 C8 D9 A7 B7 C7 D8 A6 B6 C6 A5 B5 C5 D6 A4 B4 C4 D5 A12 A16 A2 A20 A24 A29 ORT4622 Pad PT17A PT17B PT17D PT18A PT18B VDD2 PT19A PT19D PT20A PT20D PT21A PT21D PT22D PT23B PT23C VDD2 PT24A PT24B PT24C PT24D PT25A PT25B PT25C PT25D PT26A PT26B PT26C PT26D PT27A PT27B PT27C PT27D PT28A PT28B PT28C PT28D VSS VSS VSS VSS VSS VSS Function I/O I/O I/O I/O-D5 I/O VDD2 I/O I/O I/O I/O-D6 I/O I/O I/O I/O I/O VDD2 I/O I/O I/O I/O-D7 I/O I/O I/O I/O I/O I/O I/O I/O I/O-RDY/RCLK I/O I/O I/O I/O I/O I/O I/O-SECKUR VSS VSS VSS VSS VSS VSS Pin A3 A30 A8 AD1 AD31 AJ1 AJ2 AJ30 AJ31 AK1 AK29 AK3 AK31 AL12 AL16 AL2 AL20 AL24 AL29 AL3 AL30 AL8 B1 B29 B3 B31 C1 C2 C30 C31 H1 H31 M1 M31 T1 T31 Y1 Y31 A1 A31 AA28 AA4 ORT4622 Pad VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD Function VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD
Lucent Technologies Inc. Lucent Technologies Inc.
73
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Pin Information (continued)
Table 43. 432-Pin EBGA Pinout (continued) Pin AE28 AE4 AH11 AH15 AH17 AH21 AH25 AH28 AH4 AH7 AJ29 AJ3 AK2 AK30 AL1 AL31 B2 B30 ORT4622 Pad VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD Function VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD Pin C29 C3 D11 D15 D17 D21 D25 D28 D4 D7 G28 G4 L28 L4 R28 R4 U28 U4 ORT4622 Pad VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD Function VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
74
Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Pin Information (continued)
Table 44. 680-Pin PBGAM Pinout Pin D1 E2 E1 F4 F3 F2 F1 G5 G4 G2 G1 H5 H4 H2 H1 J5 J4 J3 J2 J1 K5 K4 K3 K2 K1 L5 L4 L2 L1 M5 M4 M2 M1 N5 N4 N3 N2 N1 P5 P4 P3 P2 P1 ORT4622 Pad PL1D -- -- PL1C PL1B PL1A PL2D PL2C PL2B PL2A PL3D PL3C PL3B PL3A PL4C PL4B PL4A PL5D PL5C PL5B PL5A PL6D PL6C PL6B PL6A PL7D PL7C PL7B PL7A PL8D PL8C PL8B PL8A PL9D PL9C PL9B PL9A PL10C PL10B PL10A PL11D PL11C PL11B Function I/O -- -- I/O I/O I/O I/O-A0/MPI_BE0 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O-A1/MPI_BE1 I/O I/O I/O I/O I/O I/O I/O-A2 I/O I/O I/O I/O-A3 I/O I/O I/O I/O I/O I/O Pin R5 R4 R2 R1 T5 T4 T2 T1 U5 U4 U3 U2 U1 V1 V2 V3 V4 V5 W1 W2 W4 W5 Y1 Y2 Y4 Y5 AA1 AA2 AA3 AA4 AA5 AB1 AB2 AB3 AB4 AB5 AC1 AC2 AC4 AC5 AD1 AD2 AD4 ORT4622 Pad PL11A PL12D PL12C PL12B PL13D PL13C PL13B PL13A PECKL -- PL14C PL14B PL14A PL15D PL15B PL15A PL16D PL16C PL16B PL16A PL17D PL17C PL17B PL17A PL18D PL18C PL18B PL18A -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Function I/O-A4 I/O-A5 I/O I/O I/O I/O I/O I/O I/O-ECKL -- I/O I/O I/O-MPI_CLK I/O I/O I/O-MPI_RW I/O-MPI_ACK I/O I/O I/O I/O I/O I/O I/O-MPI_BI I/O I/O I/O I/O-SECKLL -- -- -- MPI_IRQ -- -- -- -- -- -- -- -- -- -- -- 75
Lucent Technologies Inc. Lucent Technologies Inc.
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Pin Information (continued)
Table 44. 680-Pin PBGAM Pinout (continued) Pin AD5 AE1 AE2 AE3 AE4 AE5 AF1 AF2 AF3 AF4 AF5 AG1 AG2 AG4 AG5 AH1 AH2 AH4 AH5 AJ1 AJ2 AJ3 AJ4 AK1 AK2 AL1 AP4 AN5 AP5 AL6 AM6 AN6 AP6 AK7 AL7 AN7 AP7 AK8 AL8 AN8 AP8 AK9 AL9 76 ORT4622 Pad -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PCCLK -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CCLK -- -- -- -- -- -- bc (core) sys_rssigo (core) sys_dobist (core) dxn (core) dxp (core) scanen (core) scan_tstmd (core) lvds_en (core) -- -- -- Pin AM9 AP16 AK17 AL17 AM17 AN17 AP17 AP18 AN18 AN9 AP9 AK10 AL10 AM10 AN10 AP10 AK11 AL11 AN11 AP11 AK12 AL12 AN12 AP12 AK13 AL13 AM13 AN13 AP13 AK14 AL14 AM14 AN14 AP14 AK15 AL15 AN15 AP15 AK16 AL16 AN16 AM18 AL18 ORT4622 Pad -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Function ctap_refa (core) -- ref14 (core) -- reshi (core) -- reslo (core) sts_outcn (core) sts_outc (core) sts_inan (core) sts_ina (core) ctap_refb (core) sts_inbn (core) sts_inb (core) -- -- ctap_refc (core) -- -- -- sts_incn (core) sts_inc (core) sts_indn (core) sts_ind (core) -- -- -- ctap_refd (core) -- sts_outan (core) sts_outa (core) -- sts_outbn (core) sts_outb (core) -- pll_vdda (core) -- -- pll_vssa (core) rext (core) ref10 (core) -- sts_outdn (core) Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Pin Information (continued)
Table 44. 680-Pin PBGAM Pinout (continued) Pin AK18 AP19 AN19 AL19 AK19 AP20 AN20 AL20 AK20 AP21 AN21 AM21 AL21 AK21 AP22 AN22 AM22 AL22 AK22 AP23 AN23 AL23 AK23 AP24 AN24 AL24 AK24 AN25 AP25 AM25 AL25 AK25 AP26 AN26 AM26 AL26 AK26 AP27 AN27 AL27 AK27 AP28 AN28 ORT4622 Pad -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Function sts_outd (core) -- -- -- sys_clk (core) -- -- -- hdc (core) tstmode (core) -- bypass (core) tstclk (core) resetrn (core) tstshftld (core) LDC -- -- mreset (core) resettn (core) -- -- etoggle (core) ecsel (core) -- -- -- -- exdnup (core) loopbken (core) tstphase (core) INIT tstmux8s (core) tstmux5s (core) tstmux6s (core) tstmux3s (core) tstmux7s (core) tstmux4s (core) tstmux2s (core) tstmux1s (core) tstmux0s (core) addr6 (core) addr5 (core) Pin AL28 AK28 AP29 AN29 AM29 AL29 AP30 AN30 AP31 AL34 AK33 AK34 AJ31 AJ32 AJ33 AJ34 AH30 AH31 AH33 AH34 AG30 AG31 AG33 AG34 AF30 AF31 AF32 AF33 AF34 AE30 AE31 AE32 AE33 AE34 AD30 AD31 AD33 AD34 AC30 AC31 AC33 AC34 AB30 ORT4622 Pad -- -- -- -- -- -- -- -- PDONE PRESETN PPRGMN -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Function addr4 (core) addr3 (core) addr2 (core) addr1 (core) addr0 (core) -- cs_n (core) rd_wr_n (core) DONE RESET PRGM M0 rst_n (core) -- int_n (core) db4 (core) db5 (core) db6 (core) db7 (core) db0 (core) db1 (core) db2 (core) db3 (core) -- -- -- -- -- -- -- -- -- -- -- -- -- -- M1 -- -- -- -- -- 77
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Pin Information (continued)
Table 44. 680-Pin PBGAM Pinout (continued) Pin AB31 AB32 AB33 AB34 AA30 AA31 AA32 AA33 AA34 Y30 Y31 Y33 Y34 W30 W31 W33 W34 V30 V31 V32 V33 V34 U34 U33 U32 U31 U30 T34 T33 T31 T30 R34 R33 R31 R30 P34 P33 P32 P31 P30 N34 N33 N32 78 ORT4622 Pad -- -- -- -- -- -- PR18A PR18B PR18C PR18D PR17A PR17B PR17C PR17D PR16A PR16B PR16C PR15A -- PR15B PR15C PR15D PECKR PR14B PR14C PR14D PR13B PR13C PR13D PR12A PR12B PR12C PR12D PR11A PR11B PR11C PR11D PR10A PR10B PR10C PR9A PR9B PR9C Function -- -- M2 -- -- -- I/O I/O I/O I/O I/O-M3 I/O I/O I/O I/O I/O I/O I/O -- I/O I/O I/O I/O-ECKR I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O-CS1 I/O I/O I/O I/O I/O I/O I/O-CS0 I/O I/O Pin N31 N30 M34 M33 M31 M30 L34 L33 L31 L30 K34 K33 K32 K31 K30 J34 J33 J32 J31 J30 H34 H33 H31 H30 G34 G33 G31 G30 F34 F33 F32 F31 E34 E33 D34 A31 B30 A30 D29 C29 B29 A29 E28 ORT4622 Pad PR9D PR8A PR8B PR8C PR8D PR7A PR7B PR7C PR7D PR6A PR6B PR6C PR6D PR5A PR5B PR5C PR5D PR4B PR4C PR4D PR3A PR3B PR3C PR3D PR2A PR2B PR2C PR2D PR1A -- PR1B PR1C -- PR1D PRD_CFGN PT28D -- PT28C -- PT28B PT28A PT27D PT27C Function I/O I/O I/O I/O I/O I/O-RD/MPI_STRB I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O-WR I/O I/O I/O I/O I/O I/O I/O I/O -- I/O I/O -- I/O RD_CFG I/O-SECKUR -- I/O -- I/O I/O I/O I/O Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Pin Information (continued)
Table 44. 680-Pin PBGAM Pinout (continued) Pin D28 B28 A28 E27 D27 B27 A27 E26 D26 C26 B26 A26 E25 D25 C25 B25 A25 E24 D24 B24 A24 E23 D23 B23 A23 E22 D22 C22 B22 A22 E21 D21 C21 B21 A21 E20 D20 B20 A20 E19 D19 B19 A19 ORT4622 Pad PT27B PT27A PT26D PT26C PT26B PT26A PT25D PT25C PT25B PT25A PT24D PT24C PT24B PT24A PT23C PT23B PT23A PT22D PT22C PT22B PT22A PT21D PT21C PT21B PT21A PT20D PT20C PT20B PT20A PT19D PT19C PT19B PT19A PT18C PT18B PT18A PT17D PT17C PT17B PT17A PT16D PT16C PT16B Function I/O I/O-RDY/RCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O-D7 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O-D6 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O-D5 I/O I/O I/O I/O I/O I/O I/O Pin E18 D18 C18 B18 A18 A17 B17 C17 D17 E17 A16 B16 D16 E16 A15 B15 D15 E15 A14 B14 C14 D14 E14 A13 B13 C13 D13 E13 A12 B12 D12 E12 A11 B11 D11 E11 A10 B10 C10 D10 E10 A9 B9 ORT4622 Pad PT16A PECKT PT15B -- PT15A PT14D PT14C PT14A PT13D PT13C PT13B PT13A PT12D PT12C PT12B PT12A PT11D PT11C PT11B PT11A PT10D PT10C PT10B PT10A PT9C PT9B PT9A PT8D PT8C PT8B PT8A PT7D PT7C PT7B PT7A PT6D PT6C PT6B PT6A PT5D PT5C PT5B PT4D Function I/O-D4 I/O-ECKT I/O -- I/O-D3 I/O I/O I/O-D2 I/O-D1 I/O I/O I/O I/O I/O I/O I/O-D0/DIN I/O I/O I/O I/O I/O I/O I/O I/O-DOUT I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O-TDI I/O I/O I/O I/O 79
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Pin Information (continued)
Table 44. 680-Pin PBGAM Pinout (continued) Pin C9 D9 E9 A8 B8 D8 E8 A7 B7 D7 E7 A6 B6 C6 D6 A5 B5 A4 A1 A2 A33 A34 B1 B2 B33 B34 C3 C8 C12 C16 C19 C23 C27 C32 D4 D31 H3 H32 M3 M32 N13 N14 N15 80 ORT4622 Pad PT4C PT4B PT4A PT3D PT3C PT3B PT3A PT2D PT2C PT2B PT2A PT1D -- PT1C PT1B -- PT1A PRD_DATA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Function I/O I/O I/O-TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O -- I/O I/O -- I/O-TCK RD_DATA/TDO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin N20 N21 N22 P13 P14 P15 P20 P21 P22 R13 R14 R15 R20 R21 R22 T3 T16 T17 T18 T19 T32 U16 U17 U18 U19 V16 V17 V18 V19 W3 W16 W17 W18 W19 W32 Y13 Y14 Y15 Y20 Y21 Y22 AA13 AA14 ORT4622 Pad VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Function VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Pin Information (continued)
Table 44. 680-Pin PBGAM Pinout (continued) Pin AA15 AA20 AA21 AA22 AB13 AB14 AB15 AB20 AB21 AB22 AC3 AC32 AG3 AG32 AL4 AL31 AM3 AM8 AM12 AM16 AM19 AM23 AM27 AM32 AN1 AN2 AN33 AN34 AP1 AP2 AP33 AP34 C5 C30 D5 D30 E3 E4 E5 E6 E29 E30 E31 ORT4622 Pad VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 Function VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 Pin E32 F5 F30 N16 N17 N18 N19 P16 P17 P18 P19 R16 R17 R18 R19 T13 T14 T15 T20 T21 T22 U13 U14 U15 U20 U21 U22 V13 V14 V15 V20 V21 V22 W13 W14 W15 W20 W21 W22 Y16 Y17 Y18 Y19 ORT4622 Pad VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 Function VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 81
Lucent Technologies Inc. Lucent Technologies Inc.
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Pin Information (continued)
Table 44. 680-Pin PBGAM Pinout (continued) Pin AA16 AA17 AA18 AA19 AB16 AB17 AB18 AB19 AJ5 AJ30 AK3 AK4 AK5 AK6 AK29 AK30 AK31 AK32 AL5 AL30 AM5 AM30 A3 A32 B3 B4 B31 B32 C1 C2 C4 C7 C11 C15 C20 C24 C28 C31 C33 ORT4622 Pad VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD Function VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD Pin C34 D2 D3 D32 D33 G3 G32 L3 L32 R3 R32 Y3 Y32 AD3 AD32 AH3 AH32 AL2 AL3 AL32 AL33 AM1 AM2 AM4 AM7 AM11 AM15 AM20 AM24 AM28 AM31 AM33 AM34 AN3 AN4 AN31 AN32 AP3 AP32 ORT4622 Pad VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD Function VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
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Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
JC
This is the thermal resistance from junction to case. It is most often used when attaching a heat sink to the top of the package. It is defined by:
- JC = ------------------Q TJ TC
Package Thermal Characteristics Summary
There are three thermal parameters that are in common use: JA, JC, and JC. It should be noted that all the parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system airflow.
JA
This is the thermal resistance from junction to ambient (theta-JA, R-theta, etc.).
- JA = ------------------Q TJ TA
The parameters in this equation have been defined above. However, the measurements are performed with the case of the part pressed against a water-cooled heat sink to draw most of the heat generated by the chip out the top of the package. It is this difference in the measurement process that differentiates JC from JC. JC is a true thermal resistance and is expressed in units of C/W.
where TJ is the junction temperature, TA is the ambient air temperature, and Q is the chip power. Experimentally, JA is determined when a special thermal test die is assembled into the package of interest, and the part is mounted on the thermal test board. The diodes on the test chip are separately calibrated in an oven. The package/board is placed either in a JEDEC natural convection box or in the wind tunnel, the latter for forced convection measurements. A controlled amount of power (Q) is dissipated in the test chip's heater resistor, the chip's temperature (TJ) is determined by the forward drop on the diodes, and the ambient temperature (TA) is noted. Note that JA is expressed in units of C/watt.
JB
This is the thermal resistance from junction to board (JL). It is defined by:
- JB = ------------------Q TJ TB
where TB is the temperature of the board adjacent to a lead measured with a thermocouple. The other parameters on the right-hand side have been defined above. This is considered a true thermal resistance, and the measurement is made with a water-cooled heat sink pressed against the board to draw most of the heat out of the leads. Note that JB is expressed in units of C/W, and that this parameter and the way it is measured are still in JEDEC committee.
JC
This JEDEC designated parameter correlates the junction temperature to the case temperature. It is generally used to infer the junction temperature while the device is operating in the system. It is not considered a true thermal resistance, and it is defined by:
TJ - TC JC = ------------------Q
FPGA Maximum Junction Temperature
Once the power dissipated by the FPGA has been determined (see the Estimating Power Dissipation section), the maximum junction temperature of the FPGA can be found. This is needed to determine if speed derating of the device from the 85 C junction temperature used in all of the delay tables is needed. Using the maximum ambient temperature, TAmax, and the power dissipated by the device, Q (expressed in C), the maximum junction temperature is approximated by: TJmax = TAmax + (Q * JA) Table 45 lists the thermal characteristics for all packages used with the ORCA ORT4622 Series of FPGAs.
where TC is the case temperature at top dead center, TJ is the junction temperature, and Q is the chip power. During the JA measurements described above, besides the other parameters measured, an additional temperature reading, TC, is made with a thermocouple attached at top-dead-center of the case. JC is also expressed in units of C/W.
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Preliminary Data Sheet March 2000
Package Thermal Characteristics
Table 45. ORCA ORT4622 Plastic Package Thermal Guidelines
JA (C/W)
Package 432-Pin EBGA 680-Pin PBGAM 0 fpm 11 14.5 200 fpm 8.5 TBD 500 fpm 5 TBD
T = 70 C Max TJ = 125 C Max 0 fpm (W) 5 3.8
Package Coplanarity
The coplanarity limits of the ORCA Series 3/3+ packages are as follows:
s s
EBGA: 8.0 mils PBGAM: 8.0 mils
Package Parasitics
The electrical performance of an IC package, such as signal quality and noise sensitivity, is directly affected by the package parasitics. Table 46 lists eight parasitics associated with the ORCA packages. These parasitics represent the contributions of all components of a package, which include the bond wires, all internal package routing, and the external leads. Four inductances in nH are listed: LSW and LSL, the self-inductance of the lead; and LMW and LML, the mutual inductance to the nearest neighbor lead. These parameters are important in determining ground bounce noise and inductive crosstalk noise. Three capacitances in pF are listed: CM, the mutual capacitance of the lead to the nearest neighbor lead; and C1 and C2, the total capacitance of the lead to all other leads (all other leads are assumed to be grounded). These parameters are important in determining capacitive crosstalk and the capacitive loading effect of the lead. Resistance values are in m. The parasitic values in Table 46 are for the circuit model of bond wire and package lead parasitics. If the mutual capacitance value is not used in the designer's model, then the value listed as mutual capacitance should be added to each of the C1 and C2 capacitors.
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Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Package Parasitics (continued)
Table 46. ORCA ORT4622 Package Parasitics Package Type 432-Pin EBGA 680-Pin PBGAM LSW 4 3.8 LMW 1.5 1.3 RW 500 250 C1 1.0 1.0 C2 1.0 1.0 CM 0.3 0.3 LSL 3--5.5 2.8--5 LML 0.5--1 0.5--1
LSW PAD N
RW
LSL
CIRCUIT BOARD PAD
C1 LMW CM LML
C2
PAD N + 1 LSW RW C1 LSL C2
5-3862(C)r2
Figure 34. Package Parasitics
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Package Outline Diagrams
Terms and Definitions
Basic Size (BSC): Design Size: Typical (TYP): Reference (REF): Minimum (MIN) or Maximum (MAX): The basic size of a dimension is the size from which the limits for that dimension are derived by the application of the allowance and the tolerance. The design size of a dimension is the actual size of the design, including an allowance for fit and tolerance. When specified after a dimension, this indicates the repeated design size if a tolerance is specified or repeated basic size if a tolerance is not specified. The reference dimension is an untoleranced dimension used for informational purposes only. It is a repeated dimension or one that can be derived from other values in the drawing. Indicates the minimum or maximum allowable size of a dimension.
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Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Package Outline Diagrams (continued)
432-Pin EBGA
Dimensions are in millimeters.
40.00 0.10 A1 BALL IDENTIFIER ZONE
40.00 0.10
0.91 0.06
1.54 0.13 SEATING PLANE 0.20
0.63 0.07
SOLDER BALL
30 SPACES @ 1.27 = 38.10
AL AK AH AG AF AD AB Y V U T P M K H F D C B A R N L J G E AE AC AA W AJ
0.75 0.15
30 SPACES @ 1.27 = 38.10
A1 BALL CORNER
1 2
3 4
5 6
7 8
9 10
11 12
13 15 17 19 21 23 25 27 29 31 14 16 18 20 22 24 26 28 30
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Package Outline Diagrams (continued)
680-Pin PBGAM
Dimensions are in millimeters.
35.00 A1 BALL IDENTIFIER ZONE 30.00 - 0.00
+ 0.70
35.00
30.00 - 0.00
+ 0.70
1.170 0.61 0.08 SEATING PLANE 0.20 SOLDER BALL 0.50 0.10 33 SPACES @ 1.00 = 33.00 2.51 MAX
AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 11 13 15 17 19 21 23 25 27 29 31 33 10 12 14 16 18 20 22 24 26 28 30 32 34
0.64 0.15
33 SPACES @ 1.00 = 33.00
A1 BALL CORNER
5-4406(F)
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Preliminary Data Sheet March 2000
ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Notes:
Lucent Technologies Inc. Lucent Technologies Inc.
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ORCA ORT4622 FPSC Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet March 2000
Ordering Information
ORT4622 DEVICE TYPE
BC 432 TEMPERATURE RANGE NUMBER OF PINS PACKAGE TYPE
5-6435 (F).i
Table 47. Voltage Options Device ORT4622 Voltage 2.5 V/3.3 V
Table 49. Package Type Options Symbol BC BM Temperature 0 C to 70 C -40 C to +85 C Description Enhanced Ball Grid Array (EBGA) Plastic Ball Grid Array, Multilayer
Table 48. Temperature Options Symbol (Blank) I Description Commercial Industrial
Table 50. ORCA Series 3+ Package Matrix Package Device ORT4622 432-Pin EBGA BC432 CI 680-Pin PBGAM BM680 CI
Key: C = commercial, I = industrial.
For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro, or for FPGA information, http://www.lucent.com/orca E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 . JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. ORCA is a registered trademark of Lucent Technologies Inc. Foundry is a trademark of Xilinx, Inc.
Copyright (c) 2000 Lucent Technologies Inc. All Rights Reserved
March 2000 DS00-110FPGA (Replaces DS99-334FPGA)

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